MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 54

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

External Interrupt Module (IRQ)
If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0–PA3 pin latches
an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR
external interrupt sources. As long as any source is holding a PA0–PA3 pin high, an external interrupt
request is latched, and the CPU continues to execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
5.4 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused
bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
IRQR — Interrupt Request Reset Bit
IRQF — External Interrupt Request Flag
IRQE — External Interrupt Request Enable Bit
54
This write-only bit clears the external interrupt request flag.
The external interrupt request flag is a clearable, read-only bit that is set when an external interrupt
request is pending. Reset clears the IRQF bit.
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
1 = External interrupt request pending
0 = No external interrupt request pending
1 = External interrupt requests enabled
0 = External interrupt requests disabled
Address:
The BIH and BIL instructions apply only to the level on the IRQ/V
and not to the output of the logic OR function with the PA0–PA3 pins. The
state of the individual port A pins can be checked by reading the
appropriate port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether these
pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external interrupts
(PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables all
maskable interrupt requests, including external interrupt requests.
Reset:
Read:
Write:
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
$000A
IRQE
Bit 7
1
Figure 5-4. IRQ Status and Control Register (ISCR)
= Unimplemented
6
0
0
5
0
0
NOTE
R
R
4
0
0
= Reserved
IRQF
3
0
2
0
0
IRQR
PP
1
0
0
pin itself
Freescale Semiconductor
Bit 0
0
0