MC68HC705KJ1CP Freescale Semiconductor, MC68HC705KJ1CP Datasheet - Page 52

• Manufacturer Part Number: MC68HC705KJ1CP
• Description: IC MCU 4MHZ 1.2K OTP 16-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CP

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

External Interrupt Module (IRQ)
If edge-sensitive-only triggering is selected, a falling edge on the IRQ/V
request. A subsequent external interrupt request can be latched only after the voltage level on the
IRQ/V
The IRQ/V
voltage on this pin can affect the mode of operation and should not exceed V
5.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ pin input of the CPU
if enabled by the PIRQ bit in the mask option register. This capability allows keyboard scan applications
where the transitions or levels on the I/O pins will behave the same as the IRQ/V
inverted phase (logic 1, rising edge). The active state of the IRQ/V
The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are enabled by the IRQE bit
in the IRQ status and control register. The PA0–PA3 pins can be positive-edge triggered only or
positive-edge and high-level triggered.
52
$000A
Addr.
PP
pin returns to logic 1 and then falls again to logic 0.
PP
PA0
IRQ
PA3
PA2
PA1
Register Name
IRQ Status and Control
pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The
Register (ISCR)
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
See page 54.
(MOR)
PIRQ
Figure 5-2. IRQ Module I/O Register Summary
Reset:
Read:
Write:
Figure 5-1. IRQ Module Block Diagram
IRQ VECTOR FETCH
IRQE
Bit 7
1
IRQR
RESET
LEVEL-SENSITIVE TRIGGER
= Unimplemented
V
DD
(MOR LEVEL BIT)
6
0
0
D
CK
LATCH
CLR
IRQ
Q
5
0
0
R
R
4
0
0
PP
IRQF
pin is a logic 0 (falling edge).
= Reserved
PP
IRQE
IRQF
3
0
pin latches an external interrupt
DD
.
PP
2
0
0
Freescale Semiconductor
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
pin except for the
IRQR
1
0
0
Bit 0
0
0