MC68HC908JL3CDW Freescale Semiconductor, MC68HC908JL3CDW Datasheet - Page 164

• Manufacturer Part Number: MC68HC908JL3CDW
• Description: IC MCU 8MHZ 4K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL3CDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -

External Interrupt (IRQ)
Technical Data
162
NOTE:
NOTE:
The vector fetch or software clear and the return of the IRQ1 pin to logic
one may occur in any order. The interrupt request remains pending as
long as the IRQ1 pin is at logic zero. A reset will clear the latch and the
MODE1 control bit, thereby clearing the interrupt even if the pin stays
low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ1 latch.
The IRQF1 bit in the ISCR register can be used to check for pending
interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes
it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
An internal pull-up resistor to V
be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
•
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic one to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ1 latch. Writing to the ACK1 bit
prior to leaving an interrupt service routine can also prevent
spurious interrupts due to noise. Setting ACK1 does not affect
subsequent transitions on the IRQ1 pin. A falling edge that occurs
after writing to the ACK1 bit latches another interrupt request. If
the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ1 pin to logic one — As long as the IRQ1 pin is
at logic zero, IRQ1 remains active.
External Interrupt (IRQ)
DD
is connected to the IRQ1 pin; this can
MC68H(R)C908JL3
Freescale Semiconductor
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Rev. 1.1