MC68HC711E20CFN3 Freescale Semiconductor, MC68HC711E20CFN3 Datasheet - Page 165
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68HC711E20CFN3
Manufacturer Part Number
MC68HC711E20CFN3
Description
IC MCU 3MHZ 20K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711E20CFN3
Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711E20CFN3
Manufacturer:
FREESCALE
Quantity:
4 463
Company:
Part Number:
MC68HC711E20CFN3
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PORT C (OUT)
Notes:
PORT C (OUT)
NOTES:
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRB (IN)
STRA (IN)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRA (IN)
Notes:
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
NOTES:
Figure 10-13. 3-State Variation of Output Handshake Timing Diagram
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRA (IN)
STRA (IN)
E
(DDR = 1)
STRA (IN)
(DDR = 0)
STRA (IN)
(DDR = 0)
E
DDR = 1
DDR = 0
DDR = 0
PREVIOUS PORT DATA
PREVIOUS PORT DATA
Figure 10-12. Port C Output Handshake Timing Diagram
E
E
b) STRA ACTIVE AFTER PORTCL WRITE
a) STRA ACTIVE BEFORE PORTCL WRITE
b) STRA ACTIVE AFTER PORTCL WRITE
a) STRA ACTIVE BEFORE PORTCL WRITE
WRITE PORTCL
READ PORTCL
WRITE PORTCL
READ PORTCL
OLD DATA
t
t
OLD DATA
PCD
PCD
M68HC11E Family Data Sheet, Rev. 5.1
(STRA Enables Output Buffer)
t
(1)
t
1
PWD
t
PWD
(1)
1
t
PWD
PWD
NEW DATA VALID
NEW DATA VALID
t
t
DEB
DEB
NEW DATA VALID
NEW DATA VALID
t
t
DEB
DEB
t
t
PCD
PCD
"READY"
“READY”
NEW DATA VALID
t
t
AES
AES
NEW DATA VALID
“READY”
"READY"
MC68L11E9/E20 Peripheral Port Timing
t
t
t
t
t
PCH
PCH
PCH
PCH
PCH
t
t
DEB
t
DEB
t
t
AES
t
t
t
AES
PCZ
PCZ
PCZ
PCZ
PORT C OUTPUT HNDSHK TIM
t
t
DEB
DEB
165
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