DSP56F801FA80 Freescale Semiconductor, DSP56F801FA80 Datasheet

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Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F801 Rev. 17 09/2007 freescale.com ...

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Version History Rev. 17 Added revision history. Added this text to footnote any particular percent of the low pulse width.” Document Revision History Description of Change Table 3-8: “However, the high pulse width does not have to ...

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... Peripherals * includes TCS pin which is reserved for factory use and is tied to VSS Freescale Semiconductor • 8K × 16-bit words (16KB) Program Flash • 1K × 16-bit words (2KB) Program RAM • 2K × 16-bit words (4KB) Data Flash • 1K × 16-bit words (2KB) Data RAM • ...

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... General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines) • Serial Communication Interface (SCI) with two pins (or two additional GPIO lines) • Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines) 4 56F801 Technical Data, Rev. 17 Freescale Semiconductor ...

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... Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. Freescale Semiconductor 56F801 Technical Data, Rev. 17 56F801 Description ...

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... The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 6 56F801 Technical Data, Rev. 17 Freescale Semiconductor ...

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... Product Documentation The four documents listed in Table 1-1 56F801. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56F801 Chip Documentation Topic 56800E Detailed description of the 56800 family architecture, and Family Manual ...

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... Number 56F801 Technical Data, Rev. 17 Detailed Pins Description 5 Table 2-2 6 Table 2-3 2 Table 2-4 2 Table 2-5 2 Table 2-6 7 Table 2-7 4 Table 2-8 2 Table 2-9 9 Table 2-10 3 Table 2-11 6 Table 2-12 Freescale Semiconductor Table 2-1 ...

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... Other Supply Port EXTAL (GPIOB2) PLL and Clock or GPIO XTAL (GPIOB3) JTAG/OnCE™ Port * includes TCS pin which is reserved for factory use and is tied to VSS Figure 2-1 56F801 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis. Freescale Semiconductor VCAPC 56F801 1 ...

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... Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that can be programmed as an input or output pin. This I/O can be utilized when using the on-chip relaxation oscillator so the EXTAL pin is not needed. 56F801 Technical Data, Rev. 17 for normal use. SS SS. Signal Description Section 5.2. Signal Description Freescale Semiconductor ...

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... Type 6 PWMA0-5 Output 1 FAULTA0 Input (Schmitt) Freescale Semiconductor State Chip- Crystal Oscillator Output—This output should be connected to an 8MHz driven external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more ...

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... In slave mode, this pin is used to select the slave. Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can Input be individually programmed as an input or output pin. After reset, the default state is SS. 56F801 Technical Data, Rev. 17 Signal Description Freescale Semiconductor ...

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... Signal Type Pins Name 3 TD0-2 Input/Output Input/Output GPIOA0-2 Freescale Semiconductor State During Reset Input Transmit Data (TXD0)—SCI0 transmit data output Input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SCI output. ...

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... TRST may be tied to V Output Debug Event—DE provides a low pulse on recognized debug events. Table 3-1 are stress ratings only, and functional operation at the 56F801 Technical Data, Rev. 17 Signal Description through a 2.2K resistor the design through a 1K resistor. SS Freescale Semiconductor ...

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... Table 3-2 Recommended Operating Conditions Characteristic Supply voltage, digital Supply Voltage, analog Voltage difference DDA Voltage difference SSA 1 ADC reference voltage Ambient operating temperature 1. VREF must be 0.3 below V DDA Freescale Semiconductor CAUTION Symbol V V ΔV Δ & PWM ouputs DD SS Symbol Min V 3.0 ...

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... useful value to use to estimate junction JT 56F801 Technical Data, Rev Value Unit Notes 48-pin LQFP 50.6 °C/W 47.4 °C/W 39.1 °C/W 37.9 °C/W 17.3 °C/W 1.2 °C/W User Determined I/O θ W ( Freescale Semiconductor 2 2 1,2 1 ...

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... Input current high (analog inputs, V Input current low (analog inputs, V Output High Voltage ( Output Low Voltage ( Output source current Output sink current 4 PWM pin output source current 5 PWM pin output sink current Input capacitance Output capacitance Freescale Semiconductor 3.0–3.6V SSA DD DDA Symbol V IH[GPIOB(2:3)] V IL[GPIOB(2:3)] 2 ...

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... DD 56F801 Technical Data, Rev. 17 ≤ = –40° to +85°C, C 50pF A L Min Typ Max 6 — 120 130 — 102 111 — 96 102 — 2.4 2.7 3.0 2.0 2.2 2.4 — 1.7 2.0 interrupt is generated). EIO Freescale Semiconductor Unit ...

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... Active state, when a bus or signal is driven, and enters a low impedance state. • Tri-stated, when a bus or signal is placed in a high impedance state. • Data Valid state, when a signal level has reached V • Data Invalid state, when a signal level is in transition between V Freescale Semiconductor IDD Analog IDD Total Freq. (MHz) ...

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... Program information block Erase information block Erase both block 56F801 Technical Data, Rev. 17 Data3 Valid Data3 Data Data Active ERASE MAS1 NVSTR IFREN = 0 Read main memory block Program main memory block Erase main memory block Erase main memory block Freescale Semiconductor ...

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... Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. Freescale Semiconductor Table 3-7 Flash Timing Parameters ...

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... IFREN XADR XE YADR YE DIN PROG Tnvs NVSTR IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR 22 Tadh Tads Tprog Tpgs Thv Figure 3-4 Flash Program Cycle Terase Figure 3-5 Flash Erase Cycle 56F801 Technical Data, Rev. 17 Tpgh Tnvh Trcv Tnvh Trcv Freescale Semiconductor ...

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... The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry Freescale Semiconductor Tme Figure 3-6 Flash Mass Erase Cycle Table 3-10 ...

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... Recommended External Crystal Parameters MΩ 8MHz (optimized for 8MHz Figure 3-8, a typical ceramic resonator circuit is no external load capacitors should be used. Recommended Ceramic Resonator Parameters MΩ 8MHz (optimized for 8MHz 56F801 Technical Data, Rev. 17 Figure 3-8 no external load capacitors Freescale Semiconductor ...

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... PRECS bit in the PLLCR to 1. When this occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets changeover between internal and external oscillators is required at startup, internal device circuits Freescale Semiconductor 56F801 XTAL ...

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... Trim Accuracy 1. Over full temperature range 3.0–3 SSA DD DDA Symbol Min Δf — Δf/Δt — +0.1 Δf/ΔV — Δf — +0.25 T 56F801 Technical Data, Rev –40° to +85°C A Typ Max Unit + — 0.1 — %/V — % Freescale Semiconductor ...

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... Figure 3-11 Typical Relaxation Oscillator Frequency vs. Temperature Figure 3-12 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25 Freescale Semiconductor - Temperature ( C) o (Trimmed to 8MHz @ 25 C) 56F801 Technical Data, Rev. 17 External Clock Operation ...

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... SSA DD DDA Symbol 1 f osc f /2 out plls plls 56F801 Technical Data, Rev 3.0–3 –40° to +85°C A Min Typ Max — — 10 — — 100 200 /2, please refer to the OCCS chapter in the out Freescale Semiconductor Unit MHz MHz ms ms ...

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... The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. Freescale Semiconductor 3.0– ...

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... Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15 IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 3-15 External Level-Sensitive Interrupt Timing IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O 56F801 Technical Data, Rev RDA First Fetch First Fetch Freescale Semiconductor ...

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... IRQA A0–A15, PS, DS, RD, WR Figure 3-17 Recovery from Stop State Using Asynchronous Interrupt Timing IRQA A0–A15 PS, DS, RD, WR Figure 3-18 Recovery from Stop State Using IRQA Interrupt Service Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing t IRI IRQ t II 56F801 Technical Data, Rev ...

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... Figures 3-19, 3-20, — ns 3-21, 3-22 — ns Figure 3- Figure 3-22 15.2 ns Figures 3-19, 3-20, 4.5 ns 3-21, 3-22 20.4 ns Figures 3-19, 3-20, — ns 3-21, 3-22 — ns Figures 3-19, 3-20, 11.5 ns 3-21, 3-22 10.0 ns Figures 3-19, 3-20, 9.7 ns 3-21, 3-22 9.0 ns Freescale Semiconductor ...

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... MISO (Input) MOSI (Output) Figure 3-19 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 3-20 SPI Master Timing (CPHA = 1) Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– ...

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... Figure 3-22 SPI Slave Timing (CPHA = ELD Slave MSB out Bits 14– MSB in Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F801 Technical Data, Rev ELG Slave LSB out LSB ELG Slave LSB out LSB in Freescale Semiconductor ...

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... MHz. MAX 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. Freescale Semiconductor Table 3-13 Timer Timing 3.0– ...

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... ADS C — ADI E 1.00 GAIN V +10 OFFSET 56F801 Technical Data, Rev. 17 Typ Max Unit — REF — 12 Bits +/- 4 +/- 5 4 LSB +/- 0.9 +/- 1 4 LSB — 5 MHz — DDA 6 — t cycles AIC 1 — t cycles AIC 5 — 1.10 1.15 — +230 +325 mV Freescale Semiconductor 6 6 ...

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... Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms) 4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected sampling time. (1pf) Figure 3-26 Equivalent Analog Input Circuit Freescale Semiconductor Symbol Min THD ...

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... Figure 3-27 Test Clock Input Timing Diagram 38 Table 3-16 JTAG Timing 3.0–3 SSA DD DDA Symbol TRST )/2 56F801 Technical Data, Rev ≤ = –40° to +85°C, C 50pF A L Min Max Unit DC 10 MHz 100 — — ns 0.4 — ns 1.2 — ns — 26.6 ns — 23 — — Freescale Semiconductor ...

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... TDO (Output) TDO (Output ) TDO (Output) Figure 3-28 Test Access Port Timing Diagram TRST (Input) t TRST Freescale Semiconductor t DS Input Data Valid Figure 3-29 TRST Timing Diagram Figure 3-30 OnCE—Debug Event 56F801 Technical Data, Rev Output Data Valid Output Data Valid ...

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... This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801. TDO TD1 TD2 PIN 1 /SS MISO MOSI SCLK TXDO RXD0 DE Figure 4-1 Top View, 56F801 48-pin LQFP Package 40 ORIENTATION MARK PIN 37 PIN 25 PIN 1 3 56F801 Technical Data, Rev. 17 ANA4 ANA3 VREF ANA2 ANA1 ANA0 FAULTA0 SSA V DDA RESET Freescale Semiconductor ...

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... Table 4-1 56F801 Pin Identification by Pin Number Pin No. Signal Name Pin No. 1 TD0 2 TD1 3 TD2 MISO 6 MOSI 7 SCLK 8 TXD0 RXD0 12 DE Freescale Semiconductor Signal Name Pin No. 13 TCS 25 14 TCK 26 15 TMS 27 16 IREQA 28 17 TDI 29 18 VCAPC2 EXTAL 33 22 XTAL ...

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... D 0.170 0.270 E 1.350 1.450 F 0.170 0.230 G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 ° ° ° REF N 0.090 0.160 P 0.250 BSC R 0.150 0.250 S 9.000 BSC S1 4.500 BSC V 9.000 BSC V1 4.500 BSC W 0.200 REF AA 1.000 REF R L ° Freescale Semiconductor ...

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... Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Freescale Semiconductor , in °C can be obtained from the equation: J × ...

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... T )/P where CAUTION (GND) pin. /V Ceramic and tantalum capacitors tend to provide better DDA SSA. 56F801 Technical Data, Rev the temperature of the package case T pin on the controller, and from the DD and V DD Freescale Semiconductor (GND) SS ...

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... TRST should be tied low. • Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. Freescale Semiconductor layers of the PCB with approximately 100 μF, preferably with a high-grade DDA 56F801 Technical Data, Rev. 17 ...

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... V Low Profile Plastic Quad Flat Pack (LQFP) 56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) *This package is RoHS compliant. 46 Pin Package Type Count 56F801 Technical Data, Rev. 17 Ambient Frequency Order Number (MHz) 80 DSP56F801FA80 60 DSP56F801FA60 80 DSP56F801FA80E* 60 DSP56F801FA60E* Freescale Semiconductor ...

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... Freescale Semiconductor 56F801 Technical Data, Rev. 17 Electrical Design Considerations 47 ...

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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...