MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 121
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MC68HC11F1CFN4
Manufacturer Part Number
MC68HC11F1CFN4
Description
IC MCU 512 EEPROM 4MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC11F1CFN4
Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
30
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
MC68HC11F1CFN4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC11F1CFN4
Manufacturer:
FREESCALE
Quantity:
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Part Number:
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PEDGE — Pulse Accumulator Edge Control
Bit 3 — Not implemented
I4/O5 — Input Capture 4/Output Compare
RTR[1:0] — RTI Interrupt Rate Select
9.5 Computer Operating Properly Watchdog Function
9.6 Pulse Accumulator
TECHNICAL DATA
Refer to 9.6 Pulse Accumulator.
Always reads zero
Refer to 9.6 Pulse Accumulator.
These two bits determine the rate at which the RTI system requests interrupts. The
RTI system is driven by an E divided by 2
dependent of the timer prescaler. These two control bits select an additional division
factor. Refer to Table 9-5.
The clocking chain for the COP function, tapped off of the main timer divider chain, is
only superficially related to the main timer system. The CR[1:0] bits in the OPTION
register and the NOCOP bit in the CONFIG register determine the status of the COP
function. One additional register, COPRST, is used to arm and clear the COP watch-
dog reset system. Refer to SECTION 5 RESETS AND INTERRUPTS for a more de-
tailed discussion of the COP function.
The MC68HC11F1 MCUs have an 8-bit counter that can be configured to operate ei-
ther as a simple event counter, or for gated time accumulation, depending on the state
of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block dia-
gram, Figure 9-3.
In the event counting mode, the 8-bit counter is incremented by pulses on an external
pin (PAI). The maximum clocking rate for the external event counting mode is the E
clock divided by two. In gated time accumulation mode, a free-running E-clock
signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer
to Table 9-6. The pulse accumulator counter can be read or written at any time.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
TIMING SYSTEM
13
rate clock that is compensated so it is in-
9-15
64