MC68332ACPV25 Freescale Semiconductor, MC68332ACPV25 Datasheet - Page 38

• Manufacturer Part Number: MC68332ACPV25
• Description: IC MCU 32-BIT 25MHZ A MASK
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACPV25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: Q1501580

PFPAR — Port F Pin Assignment Register
3.7 Resets
3.7.1 SIM Reset Mode Selection
38
MOTOROLA
RESET:
15
The bits in this register control the function of each port F pin. Any bit cleared to zero defines the corre-
sponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request
signal or MODCLK. The MODCLK signal has no function after reset.
Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the
register is set to $FF, which defines all port F pins as interrupt request inputs. If DATA9 is cleared to
zero during reset, this register is set to $00, defining all port F pins as I/O pins.
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per-
forms resets with a combination of hardware and software. The system integration module determines
whether a reset is valid, asserts control signals, performs basic system configuration based on hard-
ware mode-select inputs, then passes control to the CPU.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU32 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition,
the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines
what happens during subsequent breakpoint assertions. The following table is a summary of reset
mode selection options.
PFPAR Field
Mode Select Pin
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 17 Port F Pin Assignments
Table 18 Reset Mode Selection
Go to: www.freescale.com
Default Function
(Pin Left High)
Port F Signal
8
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9
PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0
7
6
5
Alternate Function
(Pin Pulled Low)
4
Alternate Signal
MODCLK
3
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
2
MC68332TS/D
$YFFA1F
1
MC68332
0