COP8SDE9IMT9/NOPB National Semiconductor, COP8SDE9IMT9/NOPB Datasheet - Page 39

IC MCU EEPROM 8BIT 8K 48-TSSOP

COP8SDE9IMT9/NOPB

Manufacturer Part Number
COP8SDE9IMT9/NOPB
Description
IC MCU EEPROM 8BIT 8K 48-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Sr
Datasheet

Specifications of COP8SDE9IMT9/NOPB

Core Processor
COP8
Core Size
8-Bit
Speed
20MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
39
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SDE9IMT9
*COP8SDE9IMT9/NOPB
COP8SDE9IMT9
8.0 USART
8.1 USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
8.2 DESCRIPTION OF USART REGISTER BITS
ENU — USART CONTROL AND STATUS REGISTER (Ad-
dress at 0BA)
Bit 7
PEN
PSEL1 XBIT9/
PSEL0
(Continued)
CHL1
CHL0
ERR
FIGURE 22. USART Block Diagram
RBFL
TBMT
Bit 0
39
PEN: This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
PEN = 0
PEN = 1
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
reset.
PSEL1 = 0, PSEL0 = 0
PSEL1 = 0, PSEL1 = 1
PSEL1 = 1, PSEL0 = 0
PSEL1 = 1, PSEL1 = 1
Parity disabled.
Parity enabled.
Odd Parity (if Parity enabled)
Even Parity (if Parity enabled)
Mark(1) (if Parity enabled)
Space(0) (if Parity enabled)
20032725
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