MC68HC908GR16CFJ Freescale Semiconductor, MC68HC908GR16CFJ Datasheet - Page 142

• Manufacturer Part Number: MC68HC908GR16CFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16CFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Resets and Interrupts
13.3.2.1 Software Interrupt (SWI) Instruction
The software interrupt (SWI) instruction causes a non-maskable interrupt.
13.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
13.3.2.3 IRQ Pin
A 0 on the IRQ1 pin latches an external interrupt request.
13.3.2.4 Clock Generator (CGM)
The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or
leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register.
PLLF is in the PLL control register.
13.3.2.5 Timer Interface Module 1 (TIM1)
TIM1 CPU interrupt sources:
13.3.2.6 Timer Interface Module 2 (TIM2)
TIM2 CPU interrupt sources:
13.3.2.7 Serial Peripheral Interface (SPI)
SPI CPU interrupt sources:
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TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter value rolls over to $0000
after matching the value in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable
bit, TOIE, enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status
and control register.
TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register.
TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000
after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable
bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status
and control register.
TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM2 CPU
interrupt requests. CHxF and CHxIE are in the TIM2 channel x status and control register.
SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register
to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control
register.
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
MC68HC908GR16 Data Sheet, Rev. 5.0
NOTE
Freescale Semiconductor