MC68HC908MR8CP Freescale Semiconductor, MC68HC908MR8CP Datasheet - Page 365

• Manufacturer Part Number: MC68HC908MR8CP
• Description: IC MCU 8K FLASH 8MHZ PWM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

multiplexer — A device that can select one of a number of inputs and pass the logic level of that
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
operand — Data on which an operation is performed. Usually, a statement consists of an
oscillator — A circuit that produces a constant frequency square wave that is used by the
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
PC — See program counter (PC).
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — An oscillator circuit in which the frequency of the oscillator is
PLL — See phase-locked loop (PLL).
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
input on to the output.
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
or is suitable for processing to produce executable machine code.
connected to the power supply to provide the logic 1 output voltage.
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
computer as a timing and sequencing reference.
In a system that uses odd parity, every byte is expected to have an odd number of logic 1s.
In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of logic
1s odd for odd parity or even for even parity. A parity checker in the receiver counts the
number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte
with an incorrect number of logic 1s.
synchronized to a reference signal.
Technical Data
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