MC68HC908GZ8VFA Freescale Semiconductor, MC68HC908GZ8VFA Datasheet - Page 148

• Manufacturer Part Number: MC68HC908GZ8VFA
• Description: IC MCU 8K FLASH 8MHZ CAN 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8VFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MSCAN08 Controller (MSCAN08)
12.13.6 MSCAN08 Receiver Interrupt Enable Register
WUPIE — Wakeup Interrupt Enable
RWRNIE — Receiver Warning Interrupt Enable
TWRNIE — Transmitter Warning Interrupt Enable
RERRIE — Receiver Error Passive Interrupt Enable
TERRIE — Transmitter Error Passive Interrupt Enable
BOFFIE — Bus-Off Interrupt Enable
OVRIE — Overrun Interrupt Enable
RXFIE — Receiver Full Interrupt Enable
148
1 = A wakeup event will result in a wakeup interrupt.
0 = No interrupt will be generated from this event.
1 = A receiver warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receiver error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A bus-off event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = An overrun event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event will result in a receive interrupt.
0 = No interrupt will be generated from this event.
Address:
The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Read:
Write:
Figure 12-21. Receiver Interrupt Enable Register (CRIER)
WUPIE
$0505
Bit 7
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
RWRNIE
6
0
TWRNIE
5
0
NOTE
RERRIE
4
0
TERRIE
3
0
BOFFIE
2
0
OVRIE
1
0
Freescale Semiconductor
RXFIE
Bit 0
0