MC68HC908MR8CFA Freescale Semiconductor, MC68HC908MR8CFA Datasheet - Page 137

• Manufacturer Part Number: MC68HC908MR8CFA
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.11.4 Reaction Time Calculation
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL can become unstable. Also, always choose a capacitor with a tight
tolerance (±20 percent or better) and low dissipation.
The actual acquisition and lock times can be calculated using the
equations here. These equations yield nominal values under these
conditions:
The K factor in the equations is derived from internal PLL parameters.
K
K
8.4.2.2 Acquisition and Tracking
Inverse proportionality between the lock time and the reference
frequency
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency, see
Manual and Automatic PLL Bandwidth
clock cycles, n
tracking mode entry tolerance, ∆
ACQ
TRK
•
•
•
•
is the K factor when the PLL is configured in tracking mode. See
is the K factor when the PLL is configured in acquisition mode, and
Correct selection of filter capacitor, C
Filter Capacitor
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
Clock Generator Module (CGM)
ACQ
, is required to ascertain that the PLL is within the
t
ACQ
t
AL
t
Lock
=
=



TRK



V
---------------- -
=
f
V
---------------- -
RDV
f
DDA
RDV
DDA
t
Modes.
ACQ
, before exiting acquisition mode. A










----------------
K
+
-----------------
K
Acquisition/Lock Time Specifications
TRK
t
ACQ
Modes. A certain number of
4
AL
8
F
; see
Clock Generator Module (CGM)




8.11.3 Choosing a
Technical Data
8.4.2.3
137