MC68HC908AP64CFA Freescale Semiconductor, MC68HC908AP64CFA Datasheet - Page 148
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MC68HC908AP64CFA
Manufacturer Part Number
MC68HC908AP64CFA
Description
IC MCU 64K 8MHZ SPI 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP64CFA
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
DEMO908AP64E - BOARD DEMO FOR 908AP64DEMO908AP64 - BOARD DEMO FOR 908AP64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908AP64CFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Interface Module (TIM)
TOVx — Toggle On Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
9.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
148
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX
TCHx
OVERFLOW
COMPARE
PERIOD
OUTPUT
MC68HC908AP Family Data Sheet, Rev. 4
OVERFLOW
Figure 9-11. CHxMAX Latency
Figure 9-11
COMPARE
OUTPUT
NOTE
NOTE
OVERFLOW
shows, the CHxMAX bit takes effect in the cycle
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
Freescale Semiconductor
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