C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 163

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.10.3.Endpoint0 OUT Transactions
When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be
sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit
(E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT
packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘1’.
If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data will be split
into multiple packets. If the requested data is an integer multiple of the maximum packet size for Endpoint0 (as
reported to the host), the host will send a zero-length data packet signaling the end of the transfer.
Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive Mode. In
this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to ‘1’ if a
SETUP or IN token is received while Endpoint0 is in Receive Mode.
Endpoint0 will remain in Receive mode until:
Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been received. The
SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firm-
ware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the STALL is transmitted.
1.
2.
3.
The SIE receives a SETUP or IN token.
The host sends a packet less than the maximum Endpoint0 packet size.
The host sends a zero-length packet.
Rev. 1.1
C8051F320/1
163