MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 92

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Communications Interface (SCI)
5.6.2 Address-mark wakeup
5.7 SCI error detection
Technical Data
receiver wakeup requires a minimum of one idle frame time between
messages, and no idle time between frames within a message.
Setting the WAKE bit in SCCR1 register enables address-mark wakeup
mode. The address-mark wakeup method uses the MSB of each frame
to differentiate between address information (MSB = 1) and actual
message data (MSB = 0). All frames consist of seven information bits
(eight bits if M bit in SCCR1 = 1) and an MSB which, when set to one,
indicates an address frame. The first frames of each message are
addressing frames. Receiver logic evaluates these marked frames to
determine the receivers for which that message is intended. When a
receiver finds that the message is not intended for it, it sets the RWU bit.
Once set, the RWU control bit disables all but the necessary receivers
for the remainder of the message, thus reducing software overhead for
the remainder of that message. When the next message begins, its first
frame will have the MSB set which will automatically clear the RWU bit
and indicate that this is an addressing frame. This frame is always the
first frame received after wakeup because the RWU bit is cleared before
the stop bit for the first frame is received. This method of wakeup allows
messages to include idle times, however, there is a loss in efficiency due
to the extra bit time required for the address bit in each frame.
Four error conditions can occur during SCI operation. These error
conditions are: serial data register overrun, received bit noise, framing,
and parity error. Four bits (OR, NF, FE, and PF) in serial
communications status register 1 (SCSR1) indicate if one of these error
conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be
transferred from the receive shift register to the serial data registers
(SCDRH/SCDRL) and the registers are already full (RDRF bit is set).
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Communications Interface (SCI)
Go to: www.freescale.com
MC68HC11P2 — Rev 1.0