XC68HC705B32CFN Freescale Semiconductor, XC68HC705B32CFN Datasheet - Page 111

• Manufacturer Part Number: XC68HC705B32CFN
• Description: IC MCU 2.1MHZ 32K OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CFN

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

generated after the SWI was fetched. The SWI interrupt service routine address is specified by
the contents of memory locations $1FFC and $1FFD.
9.2.3
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
9.2.3.1
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit
(INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by
the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and
INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is
recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks
further interrupts until the present one is serviced. The external interrupt service routine address
is specified by the content of memory locations $1FFA and $1FFB.
MC68HC05B6
Rev. 4.1
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
Reset
Software interrupt (SWI)
External interrupt (IRQ)
Timer input captures
Timer output compares
Timer overflow
Serial communications
interface (SCI)
Maskable hardware interrupts
External interrupt (IRQ)
Source
RESETS AND INTERRUPTS
Table 9-2 Interrupt priorities
Register
SCSR
TSR
TSR
TSR
—
—
—
TDRE, TC, OR,
OCF1, OCF2
RDRF, IDLE
ICF1, ICF2
Flags
TOF
—
—
—
Vector address
$1FFC, $1FFD
$1FFE, $1FFF
$1FFA, $1FFB
$1FF8, $1FF9
$1FF6, $1FF7
$1FF4, $1FF5
$1FF2, $1FF3
Priority
highest
lowest
Freescale
9-7
9