HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 106
HD64F2134FA20
Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2134FA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 2 Instruction Descriptions
2.2.22
CLRMAC (CLeaR MAC register)
Operation
0
Assembly-Language Format
CLRMAC
Operand Size
—
Description
This instruction simultaneously clears registers MACH and MACL.
It is supported only by the H8S/2600 CPU.
Operand Format and Number of States Required for Execution
Note: * A maximum of three additional states are required for execution of this instruction within three states
Notes
Execution of this instruction also clears the overflow flag in the multiplier to 0.
Rev. 4.00 Feb 24, 2006 page 90 of 322
REJ09B0139-0400
Addressing
MACH, MACL
Mode
—
after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP)
between the MAC instruction and this instruction, this instruction will be two states longer.
The number of states may differ depending on the product. For details, refer to the relevant
microcontroller hardware manual of the product in question.
CLRMAC
Mnemonic
CLRMAC
Operands
—
1st byte
0
1
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
2nd byte
A
Instruction Format
Initialize Multiply-Accumulate Register
—
I
0
UI H
—
—
3rd byte
—
U
—
N
4th byte
—
Z
— —
V
States
No. of
C
2*
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