HD64F3694H Renesas Electronics America, HD64F3694H Datasheet - Page 22

• Manufacturer Part Number: HD64F3694H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3694H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69
Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 71
Figure 5.6 Example of External Clock Input ................................................................................ 71
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72
Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73
Figure 5.11 Example of Incorrect Board Design ........................................................................... 74
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 80
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration............................................................................ 88
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 97
Figure 7.3 Program/Program-Verify Flowchart ........................................................................... 99
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 102
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 109
Figure 9.2 Port 2 Pin Configuration............................................................................................ 114
Figure 9.3 Port 5 Pin Configuration............................................................................................ 117
Figure 9.4 Port 7 Pin Configuration............................................................................................ 123
Figure 9.5 Port 8 Pin Configuration............................................................................................ 126
Figure 9.6 Port B Pin Configuration........................................................................................... 130
Section 10 Timer A
Figure 10.1 Block Diagram of Timer A ..................................................................................... 132
Section 11 Timer V
Figure 11.1 Block Diagram of Timer V ..................................................................................... 138
Figure 11.2 Increment Timing with Internal Clock .................................................................... 145
Figure 11.3 Increment Timing with External Clock................................................................... 145
Figure 11.4 OVF Set Timing ...................................................................................................... 145
Figure 11.5 CMFA and CMFB Set Timing................................................................................ 146
Figure 11.6 TMOV Output Timing ............................................................................................ 146
Figure 11.7 Clear Timing by Compare Match............................................................................ 146
Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 147
Rev.5.00 Nov. 02, 2005 Page xx of xxviii