MC68HC908AP16CB Freescale Semiconductor, MC68HC908AP16CB Datasheet - Page 113
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MC68HC908AP16CB
Manufacturer Part Number
MC68HC908AP16CB
Description
IC MCU 16K FLASH 8MHZ 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP16CB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908AP16CB
Manufacturer:
MOTOROLA
Quantity:
100
Part Number:
MC68HC908AP16CB
Manufacturer:
FREESCALE
Quantity:
20 000
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7.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status
bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR
bit and clears all other bits in the register.
POR — Power-On Reset Bit
PIN — External Reset Bit
COP — Computer Operating Properly Reset Bit
ILOP — Illegal Opcode Reset Bit
ILAD — Illegal Address Reset Bit (opcode fetches only)
MODRST — Monitor Mode Entry Module Reset Bit
LVI — Low-Voltage Inhibit Reset Bit
Freescale Semiconductor
1 = Last reset caused by POR circuit
0 = Read of SRSR
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
1 = Last reset caused by COP counter
0 = POR or read of SRSR
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
0 = POR or read of SRSR
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
POR while IRQ1 = V
Address:
Reset:
Read:
Write:
$FE01
POR
Bit 7
1
Figure 7-21. SIM Reset Status Register (SRSR)
= Unimplemented
DD
PIN
6
0
MC68HC908AP Family Data Sheet, Rev. 4
COP
5
0
ILOP
4
0
ILAD
3
0
MODRST
2
0
LVI
1
0
Bit 0
0
0
SIM Registers
113
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