M30260F3AGP#U5 Renesas Electronics America, M30260F3AGP#U5 Datasheet - Page 56
![IC M16C MCU FLASH 24K 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
M30260F3AGP#U5
Manufacturer Part Number
M30260F3AGP#U5
Description
IC M16C MCU FLASH 24K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F3AGP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
1
. v
Figure 6.3 Bus Block Diagram
Table 6.1 Accessible Area and Bus Cycle
J
6
0
The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to
interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-
eral bus. Figure 6.3 shows the block diagram of the internal bus.
The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.
SFR
ROM/RAM
C
2
9
0 .
2 /
B
0
0
6
2
A
0
F
2
e
G
0 -
b
Clock
generation
circuit
o r
DMAC
1 .
2
CPU
0
u
, 5
0
p
2
CPU clock
(
0
PM20 bit = 0 (2 waits)
PM20 bit = 1 (1 wait)
PM17 bit = 0 (no wait)
PM17 bit = 1 (1 wait)
M
0
1
7
6
C
CPU address bus
2 /
CPU data bus
Accessible Area
Peripheral function
page 37
6
, A
M
1
f o
6
C
3
2 /
2
9
6
, B
M
1
6
BIU
3 CPU clock cycles
2 CPU clock cycles
1 CPU clock cycle
2 CPU clock cycles
C
2 /
6
) T
Bus Cycle
ROM
Memory address bus
Memory data bus
Serial I/O
Timer
WDT
ADC
I/O
.
.
.
.
RAM
6. Processor Mode
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