M30280F6HP#U5 Renesas Electronics America, M30280F6HP#U5 Datasheet - Page 290
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
M30280F6HP#U5
Manufacturer Part Number
M30280F6HP#U5
Description
IC M16C MCU FLASH 48K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Specifications of M30280F6HP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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e
E
1
. v
J
Table 16.5 Port specifications
6
Figure 16.12 The timing of the interrupt generation at the completion of the data receive
0
16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC
C
2
9
0 .
B
2 /
If the ES0 bit in the S1D0 register is set to "1" (I
output port. When the PED bit is set to "1" and the SCL
is set to "1". Then the setting values of P2_0 and P2_1 bits in the port P2 register are output to the I
bus, regardless of he internal SCL/SDA output signals. (SCL/SDA pins are onnected to I
circuit)
The bus data can be read by reading the port pi direction register in input mode, regardless of the setting
values of the PED and PEC bits. Table 16.5 shows the port specification.
P
P
0
0
8
n i
n i
0
P
P
4
In receive mode, ACK bit = 1 WIT bit = 0
In receive mode, ACK bit = 1 WIT bit = 1
J
G
N
N
7
2
a
2
The writing signal of the S2
o r
a
a
0 -
0
. n
1
m
m
interrupt request signal
interrupt request signal
u
2
3
e
e
0
The writing signal of
p
The writing signal of
, 1
Internal WAIT flag
Internal WAIT flag
0
I
I
2
2
(
the S00 register
the S00 register
C bus interface
C bus interface
M
2
0
ACK-BIT bit
ACK-BIT bit
1
0 register
0
6
PIN flag
PIN flag
7
C
S
S
S
S
2 /
DA
DA
CL
CL
E
E
page 268
, 8
S
S
9
0
0
0
1
1
1
1
M
7 bit
7 bit
B
B
7 clock
7 clock
1
t i
t i
6
C
f o
2 /
8
3
NOTES:
) B
8
1. Do not write to the
5
8 bit
8 bit
P
P
8 clock
8 clock
E
E
D
C
0
0
-
1
-
1
B
B
t i
t i
1)
I
2
C0
clock control register except the bit ACK-BIT.
ACK bit
2
P
P
ACK
clock
C bus interface enabled), the SDA
2
2
0
1
P
P
R
R
o
o
e
e
MM
t r
t r
0
0
g
g
-
-
-
-
1 /
1 /
t s i
t s i
i D
i D
r e
r e
functions as an output port when the PEC bit
e r
e r
t c
t c
ACK
clock
o i
o i
n
n
16. MULTI-MASTER I
P
F
P
S
S
S
S
2)
u
o
D
D
o
C
C
n
t r
t r
A
A
L
L
t c
/ I
n i
/ I
/ I
n i
/ I
o i
O
1 bit
O
O
O
1 clock
p
p
n
t u
t u
u f
u f
u f
u f
n
u f
n
n
u f
n
t c
t c
t c
t c
n
n
o i
t c
o i
o i
t c
o i
n
o i
n
n
o i
n
F
, n
, n
u
1 bit
n
p
p
t c
MM
o
o
o i
2
t r
t r
C bus INTERFACE
2
n
o
functions as an
o
C bus interface
u
u
p t
p t
t u
t u
u f
u f
n
n
c
t c
o i
o i
n
n
2
C
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