MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 94
![IC MCU 8BIT 3MHZ 44-PLCC](/photos/6/89/68924/375-44-plcc_sml.jpg)
MC68HC711D3CFNE2
Manufacturer Part Number
MC68HC711D3CFNE2
Description
IC MCU 8BIT 3MHZ 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711D3CFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711D3CFNE2
Manufacturer:
ALLEGEO
Quantity:
4 492
Company:
Part Number:
MC68HC711D3CFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Programmable Timer
8.4.4 Output Compare 1 Data Register
Use this register with OC1 to specify the data that is to be stored on the affected pin of port A after a
successful OC1 compare. When a successful OC1 compare occurs, a data bit in OC1D is stored in the
corresponding bit of port A for each bit that is set in OC1M.
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits 2–0 — Not implemented; always read 0.
8.4.5 Timer Counter Register
The 16-bit read-only timer count register (TCNT) contains the prescaled value of the 16-bit timer. A full
counter read addresses the most significant byte (MSB) first. A read of this address causes the least
significant byte (LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read returns
the full 16-bit state of the counter at the time of the MSB read cycle.
In normal modes, TCNT is read-only.
94
Address:
Address: $000E — TCNT High
Address: $000F — TCNT Low
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
OC1D7
$000D
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
0
0
0
Figure 8-9. Output Compare 1 Data Register (OC1D)
Figure 8-10. Timer Counter Registers (TCNT)
= Unimplemented
OC1D6
Bit 14
Bit 6
14
6
0
0
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
OC1D5
Bit 13
Bit 5
13
5
0
0
5
0
OC1D4
Bit 12
Bit 4
12
4
0
0
4
0
OC1D3
Bit 11
Bit 3
11
3
0
0
3
0
Bit 10
Bit 2
10
2
0
0
0
2
0
Bit 9
Bit 1
1
0
0
9
0
1
0
Freescale Semiconductor
Bit 08
Bit 0
Bit 8
Bit 0
Bit 0
0
0
0
0