MC908GR48AVFAE Freescale Semiconductor, MC908GR48AVFAE Datasheet - Page 207
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MC908GR48AVFAE
Manufacturer Part Number
MC908GR48AVFAE
Description
IC MCU 8BIT 48K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR48AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR48AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
15.4.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. Since the SPI clock is free-running, it is uncertain where the write to the SPDR
occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown
in
bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus
cycles for DIV128.
Freescale Semiconductor
Figure
15-8. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU
CAPTURE STROBE
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
SPSCK CYCLE #
FROM MASTER
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
SS; TO SLAVE
FROM SLAVE
MOSI
MISO
Figure 15-7. Transmission Format (CPHA = 1)
MSB
MSB
1
Figure
BIT 6
BIT 6
2
15-8.) The internal SPI clock in the master is a free-running
BIT 5
BIT 5
3
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
LSB
8
LSB
Transmission Formats
207
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