MC908GR60AMFAE Freescale Semiconductor, MC908GR60AMFAE Datasheet - Page 33

• Manufacturer Part Number: MC908GR60AMFAE
• Description: IC MCU 8BIT 60K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Freescale Semiconductor
$001A
$001B
$001C
$001D
$001E
$001F
$0018
$0019
Addr.
$0020
$0021
$0022
$0023
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Keyboard Status and Control
Keyboard Interrupt Enable
Timebase Module Control
ESCI Baud Rate Register
Register High (T1MODH)
Register High (T1CNTH)
TIM1 Status and Control
Configuration Register 2
Configuration Register 1
Register Low (T1CNTL)
IRQ Status and Control
Register Name
Register (INTKBSCR)
TIM1 Counter Modulo
Register (INTKBIER)
ESCI Data Register
Register (INTSCR)
Register (TBCR)
Register (T1SC)
See page 173.
See page 174.
See page 118.
See page 119.
See page 224.
See page 112.
See page 234.
See page 235.
See page 235.
See page 236.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
(CONFIG2)
(CONFIG1)
TIM1 Counter
TIM1 Counter
See page 90.
See page 91.
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
(SCDR)
(SCBR)
(1)
(1)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
COPRS
KBIE7
Bit 15
Bit 15
Bit 7
LINT
TBIF
TOF
Bit 7
R7
T7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
= Unimplemented
MCLKSEL
LVISTOP
KBIE6
TBR2
TOIE
LINR
R6
T6
14
14
6
0
0
0
0
0
0
0
0
0
0
0
6
0
1
LVIRSTD
MCLK1
TSTOP
KBIE5
SCP1
TBR1
R5
T5
13
13
5
0
0
0
0
0
0
0
0
0
1
0
5
0
1
R = Reserved
LVIPWRD
MCLK0
Unaffected by reset
KBIE4
SCP0
TRST
TBR0
R4
T4
12
12
4
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
LVI5OR3
KBIE3
KEYF
TACK
IRQF
R3
T3
11
11
R
R
3
0
0
0
0
0
0
0
0
0
0
0
3
0
1
†
U = Unaffected
TMBCLK-
SSREC
KBIE2
SCR2
ACKK
TBIE
ACK
SEL
PS2
R2
T2
10
10
Input/Output (I/O) Section
2
0
0
0
0
0
0
0
0
0
0
0
2
0
1
OSCENIN-
IMASKK
IMASK
KBIE1
SCR1
TBON
STOP
STOP
PS1
R1
T1
1
0
0
0
0
0
0
0
0
9
0
1
0
9
1
SCIBDSRC
MODEK
MODE
KBIE0
COPD
SCR0
Bit 0
Bit 8
Bit 0
Bit 8
PS0
R0
T0
R
0
0
0
0
0
1
0
0
0
0
1
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