M30262F8GP#U5 Renesas Electronics America, M30262F8GP#U5 Datasheet - Page 147
![IC M16C/TINY MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
M30262F8GP#U5
Manufacturer Part Number
M30262F8GP#U5
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M30262F4GPU3.pdf
(41 pages)
3.M30262F4GPU3.pdf
(241 pages)
Specifications of M30262F8GP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
M30262F8GP#U5M30262F8GP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30262F8GP#U5M30262F8GP#D5
Manufacturer:
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Quantity:
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Part Number:
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Clock Asynchronous Serial I/O (UART) Mode
Figure 1.15.25. Output timing of the parity error signal
Figure 1.15.26. SIM interface format
(a) Function to output a parity error signal
(b) Direct format/inverse format
complete flag
During reception, with the error signal output enable bit (bit 7 of address 037D
can output an “L” level from the T
comparing with the case in which the error signal output enable bit (bit 7 of address 037D
signed “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock.
Therefore parity error signals can be detected by a transmission completion interrupt program. Figure
1.15.25 shows the output timing of the parity error signal.
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D
and output from TxD
Figure 1.15.26 shows the SIM interface format.
(inverse)
LSB first
Transfer
Transfer
Receive
(direct)
Preliminary Specifications Rev. 0.9
TxD
TxD
clcck
Specifications in this manual are tentative and subject to change.
RxD
TxD
clock
2
2
2
2
H
H
H
L
L
L
1
0
0
2
data is output from TxD
.
ST
D0
D7
D0
Renesas Technology Corp.
X
D
D1
D6
2
D1
pin when a parity error is detected. And during transmission,
D2
D5
D2
2
. If you choose the inverse format, D
D3
D4
D3
Hi-Z
D4
D3
D4
D5
D2
D5
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D6
D1
D6
D7
D0
ST : Start bit
P : Even Parity
SP : Stop bit
D7
P
P
P
P : Even parity
16
) assigned “1”, you
SP
M16C/26 Group
7
data is inverted
16
) is as-
139
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