MC9S08GT32CFDER Freescale Semiconductor, MC9S08GT32CFDER Datasheet - Page 101
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MC9S08GT32CFDER
Manufacturer Part Number
MC9S08GT32CFDER
Description
IC MCU 32K FLASH 2K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.M68EVB908GB60E.pdf
(290 pages)
Specifications of MC9S08GT32CFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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7.1.2
This is a high-level description only. Detailed descriptions of operating modes are contained in
Section 7.3, “Functional
7.2
7.2.1
Table 7-1
Freescale Semiconductor
•
•
•
•
•
Mode 1 — Off
The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is
executed.
Mode 2 — Self-clocked (SCM)
Default mode of operation that is entered out of reset. The ICG’s FLL is open loop and the digitally
controlled oscillator (DCO) is free running at a frequency set by the filter bits.
Mode 3 — FLL engaged internal (FEI)
In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the
internal reference clock.
— FLL engaged internal unlocked is a transition state which occurs while the FLL is attempting
— FLL engaged internal locked is a state which occurs when the FLL detects that the DCO is
Mode 4 — FLL bypassed external (FBE)
In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source.
Mode 5 — FLL engaged external (FEE)
The ICG’s FLL is used to generate frequencies that are programmable multiples of the external
clock reference.
— FLL engaged external unlocked is a transition state which occurs while the FLL is attempting
— FLL engaged external locked is a state which occurs when the FLL detects that the DCO is
External Signal Description
shows the user-accessible signals available for the ICG.
Modes of Operation
to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
locked to a multiple of the internal reference.
to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
locked to a multiple of the internal reference.
Overview
Name
EXTAL
XTAL
Description."
MC9S08GB/GT Data Sheet, Rev. 2.3
External clock/oscillator input
Table 7-1. Signal Properties
Oscillator output
Function
Analog output
Reset State
Analog input
External Signal Description
101
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