R5F21217JFP#U0 Renesas Electronics America, R5F21217JFP#U0 Datasheet - Page 486

• Manufacturer Part Number: R5F21217JFP#U0
• Description: IC R8C/20 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F21217JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
0.20
REVISION HISTORY
Jun 28, 2006
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Figure 17.4 Typical Operation when Sending a Header Field;
Figure 17.5 Example of Header Field Transmission Flowchart (1) revised.
Figure 17.6 Example of Header Field Transmission Flowchart (2) revised.
Figure 17.7 Typical Operation when Receiving a Header Field;
Figure 17.8 Example of Header Field Reception Flowchart (1) revised.
Figure 17.9 Example of Header Field Reception Flowchart (2) revised.
Figure 17.10 Example of Header Field Reception Flowchart (3) revised.
Figure 17.11 Typical Operation when a Bus Collision is Detected;
17.5 Interrupt Requests, on the 2nd line;
Table 18.1 Performance of A/D converter revised.
Figure 18.1 Block Diagram of A/D Converter;
Table 18.2 One-Shot Mode Specifications, Input pin;
18.3 Sample and Hold, on the 2nd and 5th lines;
18.4 A/D Conversion Cycles added.
18.5 Internal Equivalent Circuit of Analog Input added.
18.6 Output Impedance of Sensor Under A/D Conversion added.
18.7 Notes on A/D Converter;
19. Flash Memory;
Table 19.1 Flash Memory Performance, Program and Erase Endurance;
19.2 Memory Map, on the 4th and 5th lines;
Figure 19.1 Flash Memory Block Diagram for R8C/20 Group revised.
Figure 19.2 Flash Memory Block Diagram for R8C/21 Group revised.
19.3 Functions to Prevent Rewriting of Flash Memory;
19.3.2 ROM Code Protect Function, on the 5th and 7th lines;
R8C/20 Group, R8C/21 Group Hardware Manual
“RAIC” → “TRAIC” corrected.
“RAIC” → “TRAIC” corrected.
“RAIC” → “TRAIC” corrected.
“Synch Break generation competed” added.
“ADGSEL” → “ADGSEL0” corrected.
“AN8” → “AN0” corrected.
“to 28 φ AD cycles ~ 10-bit resolution.” deleted.
“When performing ~ the microcomputer.” deleted.
“18.7 Precautions on A/D Converter” → “18.7 Notes on A/D Converter”
revised.
“19. Flash Memory Version” → “19. Flash Memory” revised.
“Program Area” → “Program ROM”
“Data Area” → “Data ROM” revised.
“(program ROM)” and “(data flash)” added.
“19.3 Functions to prevent Flash Memory from Rewriting” → “19.3
Functions to Prevent Rewriting of Flash Memory” revised.
“The ROM code ~ flash memory.” deleted.
“write 0 to the ROMCR bit” → “erase the block including the OFS
register” revised.
C - 10
Description
Summary