R5F21237KFP#U0 Renesas Electronics America, R5F21237KFP#U0 Datasheet - Page 264
R5F21237KFP#U0
Manufacturer Part Number
R5F21237KFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21237KFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
16MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21237KFP#U0R5F21237KFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.94
Figure 14.95
Timer RD General Register Ai, Bi, C1 and Di (i = 0 or 1)
Timer RD Counter 0
Timer RD Counter 1
(b15)
(b15)
(b15)
b7
NOTES:
b7
NOTE:
b7
NOTE:
1.
2. The TRDGRC0 register is not used in complementary PWM mode.
The following registers are disabled in the complementary PWM mode:
TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1
and TRDPOCR1
1.
1.
Access the TRDGRAi to TRDGRDi registers in 16-bit units. Do not access them in 8-bit units.
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
Registers TRD0 to TRD1 in Complementary PWM Mode
Mode
Registers TRDGRAi, TRDGRBi, TRDGRC1 and TRDGRDi in Complementary PWM
(b8)
(b8)
(b8)
b0
b0
b0
b7
b7
b7
Refer to Table 14.32 TRDGRji Register Functions in Com plem entary PWM Mode
Set the dead time.
Count a count source. Count operation is incremented or decremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
Select 0000h.
Count a count source. Count operation is incremented or decremented.
When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1.
(1)
(1)
Page 242 of 501
b0
b0
b0
TRDGRA0
TRDGRA1
TRDGRB0
TRDGRD0
TRDGRB1
TRDGRC1
TRDGRD1
Symbol
Symbol
Symbol
TRD0
TRD1
Function
Function
(1,2)
Function
014Bh-014Ah
015Bh-015Ah
015Dh-015Ch
0149h-0148h
014Fh-014Eh
0159h-0158h
015Fh-015Eh
0147h-0146h
0157h-0156h
Address
Address
Address
0000h to FFFFh
0000h to FFFFh
Setting Range
Setting Range
After Reset
After Reset
After Reset
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
0000h
0000h
14. Timers
RW
RW
RW
RW
RW
RW
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