MC9S08DN60CLF Freescale Semiconductor, MC9S08DN60CLF Datasheet - Page 306
![IC MCU 60K FLASH 2K RAM 48-LQFP](/photos/12/46/124624/mc9s08dn60clf_sml.jpg)
MC9S08DN60CLF
Manufacturer Part Number
MC9S08DN60CLF
Description
IC MCU 60K FLASH 2K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DN60CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DN60CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 16 Development Support
16.4.3.7
This register can be read or written at any time.
306
Reset
RWBEN
DBGEN
RWAEN
BRKEN
Field
ARM
RWA
RWB
TAG
W
7
6
5
4
3
2
1
0
R
DBGEN
Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
0 DBG disabled
1 DBG enabled
Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used
to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually
stopped by writing 0 to ARM or to DBGEN.
0 Debugger not armed
1 Debugger armed
Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
BRKEN = 0, this bit has no meaning or effect.
0 CPU breaks requested as force type requests
1 CPU breaks requested as tag type requests
Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU
break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a
begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of
CPU break requests.
0 CPU break requests not enabled
1 Triggers cause a break request to the CPU
R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0 Comparator A can only match on a write cycle
1 Comparator A can only match on a read cycle
Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
0 R/W is not used in comparison A
1 R/W is used in comparison A
R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0 Comparator B can match only on a write cycle
1 Comparator B can match only on a read cycle
Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
0 R/W is not used in comparison B
1 R/W is used in comparison B
0
7
Debug Control Register (DBGC)
ARM
0
6
Table 16-4. DBGC Register Field Descriptions
Figure 16-7. Debug Control Register (DBGC)
MC9S08DN60 Series Data Sheet, Rev 3
TAG
0
5
BRKEN
0
4
Description
RWA
0
3
RWAEN
0
2
Freescale Semiconductor
RWB
1
0
RWBEN
0
0
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