MCF54455CVR200 Freescale Semiconductor, MCF54455CVR200 Datasheet - Page 34

• Manufacturer Part Number: MCF54455CVR200
• Description: IC MPU 32BIT 200MHZ 360TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5445xr

Specifications of MCF54455CVR200

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 132
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 360-TEPBGA
• Processor Series: MCF544x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 16 KB
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, SSI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M54455EVB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 16 Channel
• On-chip Dac: 16 bit, 16 Channel
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With: M54455EVB - BOARD EVAL FOR MCF5445X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
5.13.2
5.13.3
34
1
In MII mode, n = 3; In RMII mode, n = 1
Num
E5
E6
E7
E8
—
Num
E9
Transmit Signal Timing Specifications
Asynchronous Input Signal Timing Specifications
TXCLK frequency
TXCLK to TXD[n:0], TXEN, TXER invalid
TXCLK to TXD[n:0], TXEN, TXER valid
TXCLK pulse width high
TXCLK pulse width low
CRS, COL minimum pulse width
TXCLK (Input)
RXCLK (Input)
Characteristic
TXD[n:0]
MCF5445x ColdFire
RXD[n:0]
TXEN,
TXER
Figure 20. MII Transmit Signal Timing Diagram
Figure 19. MII Receive Signal Timing Diagram
RXDV,
RXER
Characteristic
Table 22. MII Transmit Signal Timing
Table 21. Transmit Signal Timing
1
®
1
E6
Microprocessor Data Sheet, Rev. 6
35%
35%
Min
—
—
5
MII Mode
E1
E4
Valid Data
E8
Valid Data
Max
65%
65%
25
—
25
E3
E2
E7
E5
Min
1.5
35%
35%
Min
—
—
5
RMII Mode
Max
—
Max
65%
65%
50
14
—
Freescale Semiconductor
TXCLK period
Unit
t
t
TXCLK
TXCLK
MHz
Unit
ns
ns