DS89C420-ECS Maxim Integrated Products, DS89C420-ECS Datasheet - Page 26

• Manufacturer Part Number: DS89C420-ECS
• Description: IC MCU 50MHZ ULTRA HS 44-TQFP
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C420-ECS

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Figure 8. External Program Memory Access (Non-Page Mode and CD1:CD0 = 10)
Table 5. Data Memory Cycle Stretch Values
As shown in
categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on external data
memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch value is set to
1, 2, or 3, the external data-memory access is extended by 1, 2, or 3 stretch machine cycles, respectively. Note
that the first stretch value does not result in adding four system clocks to the RD / WR control signals. This is
because the first stretch uses one system clock to create additional setup time and one system clock to create
additional address hold time. When using very slow RAM and peripherals, a larger stretch value (4–7) can be
selected. In this stretch category, one stretch machine cycle (4 system clocks) is used to stretch the ALE pulse
width, one stretch machine cycle is used to create additional setup, one stretch machine cycle is used to create
additional hold time, and one stretch machine cycle is added to the RD or WR strobes.
Figure 9
(stretch value = 0), in the default stretch setting (stretch value = 1), and slow data-memory accessing
(stretch value = 4) when the system clock is in divide by one mode (CD1:CD0 = 10b).
XTAL1
ALE
PSEN
Port 0
Port 2
MD2:MD0
000
001
010
011
100
101
110
111
and
Internal Memory Cycles
Table
Figure 10
5, the stretch feature supports eight stretched external data-memory access cycles that can be
STRETCH
CYCLES
10
0
1
2
3
7
8
9
illustrate the timing relationship for external data-memory access in full speed
4X/2X, CD1,
CD0 = 100
0.5
1
2
3
4
5
6
7
RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
C1
Ext Memory Cycle
LSB Add
C2
MSB Add
26 of 47
C3
4X/2X, CD1,
CD0 = 000
10
12
14
1
2
4
6
8
C4
Data
C1
Ext Memory Cycle
LSB Add
C2
4X/2X, CD1,
CD0 = X10
MSB Add
12
16
20
24
28
2
4
8
C3
Data
C4
4X/2X, CD1,
CD0 = X11
12288
16384
20480
24576
28672
2048
4096
8192