DS89C420-ENL MAXIM [Maxim Integrated Products], DS89C420-ENL Datasheet
DS89C420-ENL
Related parts for DS89C420-ENL
DS89C420-ENL Summary of contents
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... P3.0/RXD0 10 P3.1/TXD0 11 P3.2/INT0 12 P3.3/INT1 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR 16 P3.7/RD 17 XTAL2 18 XTAL1 19 VSS 20 40-Pin DIP 6 7 DS89C420 17 18 44-Pin PLCC 44-Pin TQFP DS89C420 40 VCC 39 P0.0 38 P0.1 37 P0.2 36 P0.3 35 P0.4 34 P0.5 33 P0.6 32 P0.7 31 EA/VPP DS89C420 30 ALE/PROG 29 PSEN 28 P2.7 27 P2.6 26 P2.5 25 P2.4 24 P2.3 23 P2.2 22 P2 DS89C420 12 11 051302 ...
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... The EMI reduction feature disables the ALE signal when the processor is not accessing external memory. ORDERING INFORMATION PART PIN-PACKAGE DS89C420-MCL 40-Plastic DIP DS89C420-QCL DS89C420-ECL DS89C420-MNL 40-Plastic DIP DS89C420-QNL DS89C420-ENL MAX. CLOCK SPEED (MHz) 33 44-PLCC 33 44-TQFP 33 33 44-PLCC 33 44-TQFP ...
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... Sequencer Decoder IR Internal Control Bus Serial I/O Watchdog Timer & Power Manager Interrupt Internal Registers CPU Timer / 1Kx 8 Counters RAM Clock & Memory Reset Control DS89C420 PC SFRs AR Inc DPTR DPTR1 AR SP Address Bus 16K x 8 I/O Ports Flash ROM Loader ...
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... ALE is high when using the EMI reduction mode and during a reset condition. ALE can be enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON during external memory accesses alternate mode, this pin ( ) is used to execute the parallel program function. PROG DS89C420 FUNCTION PSEN remains low for consecutive PSEN ...
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... When software writes any port pin, the DS89C420 activates a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup ...
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... WR P3.6 RD P3.7 External Data Memory Read Strobe P3.7 External Access. Allows selection of internal or external EA program memory. Connect to ground to force the DS89C420 to use an external memory-program memory. The internal RAM is still accessible as determined by register settings. Connect use internal flash memory DS89C420 FUNCTION ...
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... Therefore, they required the same amount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two oscillator cycles but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While ...
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... RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O PORTS The DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has a latch that contains the value written by software. COUNTER/TIMERS Three 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations that can be read or written by software. The timers are controlled by other SFRs described in the “ ...
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... X 2 ALEON DME1 SPTA1 SPRA1 SPTA0 — — — EXEN2 TR2 — — T2OE — — — — — — DS89C420 BIT0 P0.0 — — — — — SEL IDLE IT0 M0 — — — — MD0 P1.0/T2 BGS — RI_0 — — ...
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... RS0 OV F1 FC3 FC2 FC1 — — — WDIF WTRF EWT — — — EX5 EX4 EX3 — — — MPX5 MPX4 MPX3 LPX5 LPX4 LPX3 DS89C420 BIT0 — — P FC0 — RWT — EX2 — MPX2 LPX2 ...
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... DS89C420 BIT0 ...
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... Special 0 Special DS89C420 BIT3 BIT2 BIT1 BIT0 Special Special ...
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... The program memory ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the DS89C420 to act as a bootloader for an external flash or NV SRAM. It also enables the use of the overlapping external program spaces. ...
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... Bank 0 00 FFFF INTERNAL MEMORY 03FF SRAM Data OR prog mem addr from 400 - 7FF 0000 4000 3FFF Flash Memory (Program) 2000 1FFF Flash Memory (Program) 0000 0000 FFFF External External Program Data Memory Memory 03FF 0000 DS89C420 ...
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... However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C420 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then be restored to access on-chip memory ...
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... Software selects the data pointer to be used by writing to the SEL bit (DPS.0). The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. ...
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... The ROM loader also has an auto-baud feature that determines which baud rate frequencies are being used for communication and sets up the baud rate generator for communication at that frequency. When the DS89C420 is powered up and has entered its user operating mode, the ROM loader mode can be invoked at any time by forcing RST = 1, ...
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... PC is available from Dallas Semicond uctor, titled “Loader 420.” Full details of the ROM loader software and its implementation are given in the DS89C420 User’s Guide. PARALLEL PROGRAMMING The DS89C420 allows parallel programming of its internal flash memory compatible with standard flash or EPROM programmers ...
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... POR default setting. Erase the option control register This operation disables the watch- dog reset function on power-up. 30h = Manufacturer ID 31h = Device ID 60h = Device extension L L FCh = Verify the option control register. Bit 3 of the DOUT is the logic value of the watchdog POR. DS89C420 ...
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... The active data pointer is always selected by the SEL (DPS.0) bit. The DS89C420 offers a programmable option that allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting the toggle-select-enable bit (TSL-DPS. logic 1. Once enabled, the SEL bit is ...
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... The DS89C420 also supports a second page mode operation with a different external bus structure that provides for fast external code fetches but uses 4 system clock cycles for data memory access ...
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... A basic internal memory cycle contains one system clock and a basic external memory cycle contains four system clocks for non-page mode operation. The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. ...
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... Figure 4. NON-PAGE MODE, EXTERNAL DATA-MEMORY ACCESS (STRETCH = 0, CD1:CD2 = 10) XTAL1 ALE PSEN RD WR Port 0 A MOVX Port 2 A MOVX Instruction Fetch MOVX Instruction 1st Machine Cycle 2nd Machine Cycle A INST A DATA A Memory Access Stretch = DS89C420 ...
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... The DS89C420 supports page mode in two external bus structures. The logic value of the page mode select bits in the ACON register determines the external bus structure and the basic memory cycle in the number of system clocks ...
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... P0: Lower address byte. P2: The upper address byte is multiplexed with the data byte. 4 Note: This setting affects external code fetches only; accessing the external data memory requires 4 clock cycles, regardless of page hit or miss DS89C420 ...
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... P2, and uses P0 for the least significant address byte. This bus structure is used to speed up external code fetches only. External data-memory access cycles are identical to the non-page mode except for the different signals on P0 and P2. Figure 7 illustrates the memory cycle for external code fetches DS89C420 ...
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... MOVX executed MSBAdd LSB Add Page Miss Data Inst MSB LSB MSB LSB MSB Page Miss Data Access MOVX executed Data MSBAdd LSB Add MSBAdd Data Access Page Miss next instruction Data Inst LSB Add Data Access DS89C420 PAGES=00 PAGES=01 PAGES=10 ...
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... Port 2 STRETCH EXTERNAL DATA MEMORY CYCLE IN PAGE MODE The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle in page mode operation just like non-page mode operation. The following tables summarize the stretch values and their effects on the external MOVX- memory bus cycle and the control signals’ ...
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... PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X/2X, CD1, 4X/2X, CD1, CD0 = 100 CD0 = 000 0 DS89C420 4X/2X, CD1, 4X/2X, CD1, CD0 = X10 CD0 = X11 1 1024 3 3072 7 7168 11 11,264 15 15,360 19 19,456 23 23,552 27 27,648 4X/2X, CD1, 4X/2X, CD1, CD0 = X10 ...
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... In this stretch category, two stretch cycles are used to create additional setup (the ALE pulse width is also stretched by one stretch cycle fo r page miss) and one stretch cycle is used to create additional hold time. The following timing diagrams illustrate the external data-memory access at divide by 1 system clock mode (CD1:CD0 = 10b DS89C420 ...
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... LSB Addr MSB Addr LSB Addr Memory Access (Stretch = Data Inst LSB Addr LSB Addr LSB Addr Data Inst Inst LSB Addr LSB Addr LSB Addr Data Inst Inst LSB Addr LSB Addr LSB Addr DS89C420 Inst Inst Inst ...
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... Memory Access (Stretch = 4) MOVX Instruction (Page hit) 1st 2nd 3rd 4th 5th Cycle Cycle Cycle Cycle Inst LSB Memory Access (Stretch = DS89C420 9th Cycle Inst Inst Data LSB LSB LSB 9th Cycle Inst Inst Inst Data LSB LSB LSB LSB ...
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... INTERRUPTS The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power- fail, are controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt enable register (IE.7). Setting logic 1 allows individual interrupts to be enabled. Setting logic 0 disables all interrupts regardless of the individual interrupt enable settings ...
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... Unless marked in Table 12, all of these flags must be cleared by software. TIMER/COUNTERS Three 16-bit timers are incorporated in the DS89C420. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 13 summarizes the timer functions. ...
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... If Timer 2 is used as a baud rate generator or clock output, its time base is fixed at divide by 2, regardless of the setting of its timer mode bits. For details of operation, refer to “Programmable Timers” in the DS89C420 User’s Guide. TIMER 0 ...
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... Page Mode Select Bit 0 Page Mode Select Bit 1 Page Mode Enable Program Memory Size Select Bit 0 Program Memory Size Select Bit 1 Program Memory Size Select Bit 2 Program RAM Enable Flash Command Bit 0 Flash Command Bit 1 Flash Command Bit 2 Flash Command Bit DS89C420 ...
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... CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset. When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5:SWB) is also set, the system forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts ...
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... interrupt is generated if the corresponding power- fail PFW transitions below V CC falls below reset is issued internally to halt program CC RST is first applied to the DS89C420, the processor is held in reset until DS89C420 System MUX Clock Selector , and can only be cleared PFW ...
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... When the DS89C420 enters stop mode, the bandgap, reset comparator, and power- fail interrupt comparator are automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This is the lowest power mode. If BGS is set to a logic 1, the bandgap reference, reset comparator, and the power- fail comparator are powered up, although in a reduced fashion, while in stop mode ...
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... OSCILLATOR FAIL DETECT The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. The circuit is enabled by setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit is only cleared from a logic logic power-fail reset or by software ...
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... In the case when the serial port is being used to receive or transmit data it is very important to validate an attempted change in the clock-divide control bits (read CD1 and CD0 to verify write was allowed) before proceeding with low-power program functions DS89C420 ...
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... T2MH, T2M = 0. 0.5 2 — — 12,288 4,096 1,024 2,048 DS89C420 OSC. CYCLES OSC. CYCLES PER PER SERIAL SERIAL PORT PORT CLOCK CLOCK MODE 2 MODE 0 SM2 = 0 SM2 = 1 SMOD = 0 SMOD = — — 12,288 ...
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... SERIAL I/O The DS89C420 provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1) and has duplicate control functions included in new SFR locations. ...
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... UNITS NOTES 4.5 5.0 5.5 V 4.2 4.375 4.6 V 3.95 4.125 4.35 V 100 150 -0.3 +0 0.15 0.45 V 0.15 0.45 V 2.4 V 2.4 V 2.4 V 2.4 V -55 µA -650 µA -10 +10 µA -300 +300 µA 50 170 k DS89C420 12 ...
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... For these applications, it may be desirable to use a more accurate external reset. 14) Guaranteed by design. = 5.5V. All other pins disconnected. CC and V overlap, the design of the hardware makes it such that this PFW RST DS89C420 = RST = 5.5V. All other CC = 5.5V, RST at ground MIN RST ...
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... CLCL CLCL 0. 0. CLCL CLCL t t STC4 STC4 0. 0. CLCL CLCL t t STC4 STC4 2. CLCL 1. 0. CLCL CLCL CLCL CLCL - CLCL CLCL DS89C420 UNITS NOTES MAX 33 MHz 2. CLCL CLCL ...
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... CLCL CLCL t t STC1 STC1 CLCL 2. CLCL + t STC1 CLCL t STC1 - 16 3. CLCL CLCL + STC1 STC1 DS89C420 UNITS NOTES MAX CLCL CLCL 3. CLCL CLCL STC1 CLCL 2 ...
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... STC2 STC2 STC2 STC2 1. CLCL CLCL t t STC2 STC2 1. CLCL CLCL t t STC5 STC5 - STC2 STC2 STC2 STC2 DS89C420 UNITS NOTES MAX 0. CLCL STC2 STC2 ...
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... and CTM) in the CLCL STC2 STC3 STC4 ) ( CLCL CLCL CLCL PSEN WR ) are tested with a capacitance RD DS89C420 t STC5 ) (t ) CLCL and is RD ...
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... AVLL3 t LLAX3 t t PLPH RLRH t PLIV t LLDV t AVDV0 t t AVIV0 RLDV LSB MOVX LSB DATA t AVWL2 t AVDV2 MSB MSB LLAX2 t t PLAZ WHLH t LLWL t WLWH t AVWL0 t RHDX t WHQX t t RHDZ QVWX OPCODE LSB LSB DATA t AVIV2 MSB MSB DS89C420 ...
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... WHLH t t LLAX2 LLAX t WHQX t QVWX t PXIX t WLWH t t AVWL2 PLIV DATA OPCODE LSB MSB LSB MSB t LLAX2 t t WHLH PLAZ t LLWL t WLWH t AVWL0 t t WHQX RHDX LSB LSB t RHDZ t AVIV2 MSB OPCODE MSB DS89C420 t QVWX DATA ...
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... XHQX XHDX 0 t XHDV UNITS -40°C to +85°C)* A VARIABLE MAX MIN MAX 12t CLCL 4t CLCL 10t - 100 CLCL CLCL CLCL t - 100 CLCL 0 0 200 10t CLCL 40 3t CLCL DS89C420 MAX 100 - 50 ...
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... TDX CLOCK = XTAL FREQ/12 ALE PSEN WRITE TO SBUF RXD DATA OUT TXD CLOCK TI WRITE TO SCON TXD CLOCK TO CLEAR RI RXD DATA IN TXD CLOCK R1 t XHQX XLXL XHDX 1/(XTAL FREQ/12 DS89C420 TRANSMIT RECEIVE D7 ...
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... CLCL t 48t DVGL CLCL t 48t GHDX CLCL t 85 GLGH t AVQV t ELQV t 0 EHQZ t 10 GHGL DS89C420 = -40°C to +85°C) (Note 1) A MAX UNITS NOTES ms t CLCL = +21°C to +27°C) A TYP MAX UNITS 6 MHz 100 48t CLCL 48t CLCL 48t CLCL ...
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... PDIP (600MIL) PKG 40-PIN DIM MIN MAX A — 0.200 A1 0.015 — A2 0.140 0.160 b 0.014 0.022 c 0.008 0.012 D 1.980 2.085 E 0.600 0.625 E1 0.530 0.555 e 0.090 0.110 L 0.115 0.145 eB 0.600 0.700 56–G5000–000 Dimensions are in inches (in DS89C420 ...
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... PLCC NOTES: 1) Pin 1 identifier to be located in zone indicated. 2) Controlling dimensions are in inches (in DS89C420 ...
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... TQFP DS89C420 ...
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... REVISION HISTORY 1) Original issue, 092200. 2) Added errata, 122601. (See 3) Official product introduction release, 042702. http://www.maxim- ic.com/errata for more details.) DS89C420 ...