DS89C420-MNL Maxim Integrated Products, DS89C420-MNL Datasheet - Page 32

• Manufacturer Part Number: DS89C420-MNL
• Description: IC MCU ULTRA 33MHZ HP 40-DIP
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C420-MNL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Table 9. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 10)
Table 10. Page Mode 2, Data Memory Cycle Stretch Values (Pages1:Pages0 = 11)
As shown in the previous tables, the stretch feature supports eight stretched external data-memory access cycles
that can be categorized into three timing groups. When the stretch value is cleared to 000b, there is no stretch on
external data-memory access and a MOVX instruction is completed in two basic memory cycles. When the stretch
value is set to 1, 2, or 3, the external data memory access is extended by 1, 2, or 3 stretch memory cycles,
respectively. Note that the first stretch value does not result in adding four system clocks to the control signals. This
is because the first stretch uses one system clock to create additional address setup and data bus float time, and
one system clock to create additional address and data hold time. When using very slow RAM and peripherals, a
larger stretch value (4–7) can be selected. In this stretch category, two stretch cycles are used to create additional
setup (the ALE pulse width is also stretched by one stretch cycle for page miss) and one stretch cycle is used to
create additional hold time. The following timing diagrams illustrate the external data-memory access at divide-by-1
system clock mode (CD1:CD0 = 10b).
MD2:MD0
MD2:MD0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
STRETCH
STRETCH
CYCLES
CYCLES
10
10
0
1
2
3
7
8
9
0
1
2
3
7
8
9
4X/ 2X , CD1,
4X/ 2X , CD1,
CD0 = 100
CD0 = 100
0.5
0.5
1
2
3
4
5
6
7
1
2
3
4
5
6
7
RD / WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
RD / WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS)
32 of 47
4X/ 2X , CD1,
4X/ 2X , CD1,
CD0 = 000
CD0 = 000
10
12
14
10
12
14
1
2
4
6
8
1
2
4
6
8
4X/ 2X , CD1,
4X/ 2X , CD1,
CD0 = X10
CD0 = X10
12
16
20
24
28
12
16
20
24
28
2
4
8
2
4
8
4X/ 2X , CD1,
4X/ 2X , CD1,
CD0 = X11
CD0 = X11
12,288
16,384
20,480
24,576
28,672
12,288
16,384
20,480
24,576
28,672
2048
4096
8192
2048
4096
8192