SAF-XC164CM-8F20F AA Infineon Technologies, SAF-XC164CM-8F20F AA Datasheet - Page 27
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SAF-XC164CM-8F20F AA
Manufacturer Part Number
SAF-XC164CM-8F20F AA
Description
IC MCU 16BIT FLASH TQFP-64-8
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC164CM-4F20F_AA.pdf
(70 pages)
Specifications of SAF-XC164CM-8F20F AA
Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 14x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
For Use With
B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CMMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SAF-XC164CM-8F20FAACT
SAF-XC164CM-8F20FAACT
SAF-XC164CM-8F20FAAINCT
SAF-XC164CM-8F20FAACT
SAF-XC164CM-8F20FAAINCT
XC164CM
Derivatives
Functional Description
3.4
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC164CM. The user software running on the XC164CM can thus
be debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals are realized as alternate
functions on Port 3 pins.
Data Sheet
25
V1.4, 2007-03