SAF-XC164CM-8F40F AA Infineon Technologies, SAF-XC164CM-8F40F AA Datasheet - Page 17

• Manufacturer Part Number: SAF-XC164CM-8F40F AA
• Description: IC MCU 16BIT FLASH TQFP-64-8
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CM-8F40F AA

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-LQFP-64
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 6.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 64.0 KByte
• For Use With: B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CMMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SAF-XC164CM-8F40FAACT; SAF-XC164CM-8F40FAACT; SAF-XC164CM-8F40FAAINCT

XC164CM
Derivatives
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC164CM is configured in a von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed byte wise or word wise. Portions of the
on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, or data is read from or written to peripherals on the LXBus (such as
TwinCAN). The system bus allows concurrent two-way communication for maximum
transfer performance.
1)
32/64/128 Kbytes of on-chip Flash memory
store code or constant data. The on-chip
Flash memory is organized as four 8-Kbyte sectors and up to three 32-Kbyte sectors.
2)
Each sector can be separately write protected
, erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A password sequence
temporarily unlocks protected areas. The Flash module combines very fast 64-bit one-
cycle read accesses with protected and efficient writing algorithms for programming and
erasing. Thus, program execution out of the internal Flash results in maximum
performance. Dynamic error correction provides extremely high read data security for all
read accesses.
Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector
typically takes 200 ms (500 ms max.).
2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
1)
0/2/4 Kbytes
of on-chip Data SRAM (DSRAM) are provided as a storage for general
user data. The DSRAM is accessed via the DMU and is therefore optimized for data
accesses. DSRAM is not available in the XC164CM-4F derivatives.
1) Depends on the respective derivative. See
Table 1 “XC164CM Derivative Synopsis” on Page
6.
2) Each two 8-Kbyte sectors are combined for write-protection purposes.
Data Sheet
15
V1.4, 2007-03