SAK-C868-1SR BA Infineon Technologies, SAK-C868-1SR BA Datasheet - Page 64

• Manufacturer Part Number: SAK-C868-1SR BA
• Description: IC MCU 8BIT 8KB RAM TSSOP-38-1
• Manufacturer: Infineon Technologies
• Series: C5xx/C8xxr

Specifications of SAK-C868-1SR BA

• Core Processor: C800
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: RAM
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SAKC8681SRBAXT; SP000014357

SFR SCUWDT) consecutively. This double instruction sequence has been implemented
to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and
power-down mode of the processor (see section "Power Saving Modes"). It is not
possible to use the idle mode in combination with the watchdog timer function.
Therefore, even the watchdog timer cannot reset the device when one of the power
saving modes has been entered accidentally.
The time period for an overflow of the Watchdog Timer is programmable in two ways :
The period P
therefore be determined by the following formula:
Table 14
certain module clock. Some numbers are rounded to 3 significant digits.
Table 14
Reload value
in WDTREL
FF
7F
00
For safety reasons, the user is advised to rewrite WDTCON each time before the
Watchdog Timer is serviced.
Data Sheet
– the input frequency to the Watchdog Timer can be selected via bit WDTIN in
– the reload value WDTREL for the high byte of WDT can be programmed in register
H
H
H
register WDTCON to be either f
WDTCON.
lists the possible ranges for the watchdog time which can be achieved using a
WDT
Watchdog Time Ranges
between servicing the Watchdog Timer and the next overflow can
P
Prescaler for f
2 (WDTIN = ‘0’)
40 MHz
12.8 µs
1.65 ms 3.3 ms
3.28 ms 6.55 ms 8.19 ms 209.7 ms 419.4 ms 524 ms
WDT
=
2
20 MHz
25.6 µs
(1 +WDTIN*6)
SYS
SYS
/2 or f
64
16 MHz
32.0 µs
4.13 ms
* (2
SYS
f
/128.
16
SYS
- WDTREL * 2
128 (WDTIN = ‘1’)
40 MHz
819.2 µs 1.64 ms 2.05 ms
105.7 ms 211.3 ms 264 ms
8
)
20 MHz
V 1.0, 2003-05
16 MHz
C868
[0.1]