MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 29

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TAP controller (see Figure 12). The shift registers serve
as transmit-and-receive data buffers for a debugger.
From a JTAG perspective, shift registers are user-
defined optional data registers. The bypass register
and the instruction register, for example, are realized
as a set of shift-register-based elements connected in
parallel between a common serial input (TDI) and a
common serial output (TDO). The instruction register,
through the TAP controller, selects one of the registers
to form an active serial path.
The maximum TCK clock frequency must be below
1/8 of the system clock frequency to work properly.
The TAP operates asynchronously with on-chip sys-
tem logic and may be affected by the timing relation-
Figure 12. JTAG Interface Block Diagram
PO.1/TMS
PO.3/TCK
PO.2/TDI
______________________________________________________________________________________
TO DEBUG
DV
DV
DV
ENGINE
DDIO
DDIO
DDIO
POWER-ON
RESET
WRITE
16-Bit RISC Microcontroller-Based
READ
Smart Data-Acquisition Systems
7 6 5
INSTRUCTION REGISTER
CONTROLLER
SYSTEM PROGRAMMING REGISTER
DEBUG REGISTER
SHADOW REGISTER
TAP
4 3 2
BYPASS
4 3 2
ship between the on-chip state machines and the
TAP. The on-chip state machines are clocked by the
system clock.
The four digital I/Os that form the TAP module are
described as follows:
• TDO—Serial output signal for test instruction and
• TDI—Serial input signal for test instruction and data.
1 0 S1 S0
UPDATE-DR
UPDATE-DR
data. Data is driven out only on the falling edge of
TCK and is forced in an inactive state when it is idle.
This signal is used to serially transfer internal data to
the host. Data is transferred LSB first.
Data should be driven in only on the rising edge of
TCK. This signal is used to serially transfer data from
2
1 0
1 0
MAXQ7665A–MAXQ7665D
DV
DDIO
PO.0/TDO
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