MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 30

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
• TCK—Serial clock for the test logic.
• TMS—Test mode selection. Test signals received at
The MAXQ7665A–MAXQ7665D provide eight general-
purpose digital I/Os (GPIOs). All GPIOs have an addi-
tional special function (SF), such as a timer
input/output, or TAP signal for JTAG communication.
For example, the state of pin P0.6/T0 can be pro-
grammed to depend on timer channel 0 logic. When
programmed as a port, each I/O is configurable for
high-impedance or weak pullup to DV
up, each GPIO is configured as an input with pullups to
DV
enabled and should be turned off before normal opera-
tion. In addition, each GPIO can be programmed to
cause an interrupt (on falling or rising edges). In stop
mode, any interrupt can be used to wake up the device.
The data input/output direction in a port is indepen-
dently controlled by the port direction register (PD).
Each I/O within the port can be individually set as an
output or input. The port output register (PO) contains
the current state of the logic output buffers. When an
Figure 13. Digital I/O Circuitry
30
DDIO
the host to the internal TAP module shift registers.
Data is transferred LSB first.
TMS are sampled at the rising edge of TCK and
decoded by the TAP controller to control the test
operation.
_______________________________________________________________________________________
. Note that at power-up, the JTAG function is
General-Purpose Digital I/Os
SF DIRECTION
SF OUTPUT
SF ENABLE
FLAG
SF INPUT
PI0._ OR
PD0._
PO0._
MAXQ7665A–MAXQ7665D
INTERRUPT
FLAG
CIRCUIT
DETECT
DDIO
. At power-
PD
PO
EIEO._
EIES._
I/O PAD
I/O is configured as an output, writing to the PO register
controls the output logic state. Reading the PO register
shows the current state of the output buffers, indepen-
dent of the data direction. The port input register (PI) is
a read-only register that always reflects the logic state
of the I/Os. When an I/O is configured as an input, writ-
ing to the PO register enables/disables the pull-up
resistor. Refer to the MAXQ7665/MAXQ7666 User’s
Guide for more detailed information.
The MAXQ7665A–MAXQ7665D contain only one port
(P0). It is a bidirectional 8-bit I/O port, which contains
the following features:
• Schmitt trigger input circuitry with software-selec-
• Software-selectable push-pull CMOS output drivers
• Software-selectable open-drain output drivers capa-
• Falling or rising edge interrupt capability
• All I/Os contain an additional special function, such as
table high-impedance or weak pullup to DV
capable of sinking and sourcing 1.6mA
ble of sinking 1.6mA
a logic input/output for a timer channel. Selecting an
I/O for a special function alters the port characteristics
of that I/O (refer to the MAXQ7665/MAXQ7666 User’s
Guide for more details). Figure 13 illustrates the func-
tional blocks of an I/O.
DV
GNDIO
DDIO
DV
DDIO
400kΩ
Port Characteristics
P0._
DDIO