MCP6G03-E/P Microchip Technology, MCP6G03-E/P Datasheet - Page 21
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MCP6G03-E/P
Manufacturer Part Number
MCP6G03-E/P
Description
IC GAIN BLOCK 1.8V 1CH 8-DIP
Manufacturer
Microchip Technology
Datasheet
1.MCP6G01UT-EOT.pdf
(38 pages)
Specifications of MCP6G03-E/P
Amplifier Type
General Purpose
Number Of Circuits
1
Output Type
Rail-to-Rail
Slew Rate
4.5 V/µs
-3db Bandwidth
900kHz
Current - Input Bias
1pA
Voltage - Input Offset
1000µV
Current - Supply
110µA
Current - Output / Channel
20mA
Voltage - Supply, Single/dual (±)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Gain Bandwidth Product
-
R
impedance voltage source. The power supply driving
the V
0.1Ω to maintain reasonable gain accuracy.
4.3
The MCP6G03 is a single amplifier with chip select
(CS). When CS is high, the internal op amp is shut
down and its output placed in a high-Z state. The
resistive ladder is always connected between V
V
resistance will be 350 kΩ (typ.), with a path for output
signals to appear at the input. The supply current at
V
ladder resistors; it also includes current from the CS pin
to V
is left floating, the amplifier may not operate properly.
Figure 1-2
voltage and supply current response to a CS pulse.
4.4
The amplifier can be set to the gains +1 V/V, +10 V/V,
and +50 V/V using one input pin (GSEL). At the same
time, different compensation capacitors are selected to
optimize the bandwidth vs. slew rate trade-off (see
Table
using a GPIO pin on a microcontroller and
shows how to hard wire the gain (i.e., using PCB
wiring).
TABLE 4-2:
© 2006 Microchip Technology Inc.
+1 V/V
+10 V/V
+50 V/V
Note 1:
OUT
SS
LAD
Gain
SS
includes the current through the load resistor and
SS
; even in shutdown. This means that the output
is intended to be driven at the V
4-1).
. When CS is low, the amplifier is enabled. If CS
2:
pin should have an output impedance less than
MCP6G03 Chip Select (CS)
Gain Select (GSEL)
Table 4-2
See Section 4.8.1 “Driving the Gain
Select Pin with a Microcontroller GPIO
Pin”.
See Section 4.8.2 “Driving the Gain
Select Pin with a PWM Signal”
and
Output PIC’s V
Digital Output High-Z (Notes 1)
Output V
Digital Output driven Low
Digital Output driven High
Figure 2-43
MCU DRIVEN GAIN
SELECTION
DD
shows how to change the gain
/2 PWM signal (Notes 2)
MCU Pin’s State
REF
show how the output
at V
DD
/2
SS
pin by a low
Table 4-3
SS
and
MCP6G01/1R/1U/2/3/4
TABLE 4-3:
4.5
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6G01/1R/1U/2/3/4
family of SGAs
load capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
When driving large capacitive loads with these SGAs
(i.e., > 60 pF), a small series resistor at the output
(R
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-5:
Capacitive Loads.
Figure 4-6
different capacitive loads. After selecting R
circuit, double check the resulting frequency response
peaking and step response overshoot on the bench.
Modify R
all gains.
Note 1:
Selected Gain
ISO
+10 V/V
+50 V/V
V
+1 V/V
IN
in
ISO
Capacitive Load and Stability
Figure
The GSEL pin floats to mid-supply
(V
needed.
’s value until the response is reasonable at
gives recommended R
DD
MCP6G0X
(Figure 2-30
4-5) improves the internal amplifier’s
/2); a bypass capacitor may be
Open Circuit (Note 1)
Low impedance source at V
Tied to GND (0V)
Tied to V
HARD WIRED GAIN
SELECTION
Possible GSEL Drivers
SGA Circuit for Large
DD
and
R
ISO
Figure
DS22004B-page 21
ISO
2-34). As the
C
ISO
values for
L
V
DD
OUT
for your
/2