LT1499CS#TRPBF Linear Technology, LT1499CS#TRPBF Datasheet - Page 17

• Manufacturer Part Number: LT1499CS#TRPBF
• Description: IC OP-AMP R-R IN/OUT QUAD 14SOIC
• Manufacturer: Linear Technology
• Series: C-Load™r

Specifications of LT1499CS#TRPBF

• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Slew Rate: 6 V/µs
• Gain Bandwidth Product: 10.5MHz
• Current - Input Bias: 250nA
• Voltage - Input Offset: 200µV
• Current - Supply: 1.8mA
• Current - Output / Channel: 30mA
• Voltage - Supply, Single/dual (±): 2.2 V ~ 36 V, ±1.1 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -

APPLICATIONS INFORMATION
Rail-to-Rail Input and Output
The LT1498/LT1499 are fully functional for an input and
output signal range from the negative supply to the posi-
tive supply. Figure 1 shows a simplifi ed schematic of the
amplifi er. The input stage consists of two differential am-
plifi ers, a PNP stage (Q1/Q2) and an NPN stage (Q3/Q4)
which are active over different ranges of input common
mode voltage. A complementary common emitter output
stage (Q14/Q15) is employed allowing the output to swing
from rail-to-rail. The devices are fabricated on Linear
Technology’s proprietary complementary bipolar process
to ensure very similar DC and AC characteristics for the
output devices (Q14/Q15).
The PNP differential input pair is active for input com-
mon mode voltages, V
to approximately 1.3V below the positive supply. As V
moves further toward the positive supply, the transistor
(Q5) will steer the tail current, I
(Q6/Q7) activating the NPN differential pair, and the PNP
differential pair becomes inactive for the rest of the input
common mode range up to the positive supply.
+IN
–IN
V
V
+
–
R6
R7
D5
D6
CM
, between the negative supply
Q4
Q7
D1
D2
1
Q3
, to the current mirror
Figure 1. LT1498 Simplifi ed Schematic Diagram
Q5
Q6
V
BIAS
Q1
D3
D4
CM
Q2
I
1
The output is confi gured with a pair of complementary
common emitter stages that enables the output to swing
from rail to rail. Capacitors (C1 and C2) form local
feedback loops that lower the output impedance at high
frequencies.
Input Offset Voltage
The offset voltage changes depending upon which input
stage is active. The input offsets are random, but are
trimmed to less than 475μV. To maintain the precision
characteristics of the amplifi er, the change of V
entire input common mode range (CMRR) is guaranteed
to be less than 425μV on a single 5V supply.
Input Bias Current
The input bias current polarity also depends on the input
common mode voltage, as described in the previous sec-
tion. When the PNP differential pair is active, the input bias
currents fl ow out of the input pins; they fl ow in opposite
direction when the NPN input stage is active. The offset error
due to input bias current can be minimized by equalizing
the noninverting and inverting input source impedances.
This will reduce the error since the input offset currents
are much less than the input bias currents.
Q10
Q11
Q9
R3
R1
Q12
Q8
R2
R4
V
Q13
–
R5
OUTPUT BIAS
LT1498/LT1499
C
C
BUFFER
AND
C2
C1
14989 F01
Q15
Q14
OS
OUT
over the
17
14989fg