HCPL-7520-560 Avago Technologies US Inc., HCPL-7520-560 Datasheet - Page 12

• Manufacturer Part Number: HCPL-7520-560
• Description: OPTOCOUPLER AMP 100KHZ IEC 8-SMD
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-7520-560

• Amplifier Type: Isolation
• Number Of Circuits: 1
• -3db Bandwidth: 100kHz
• Current - Input Bias: 600nA
• Voltage - Input Offset: 600µV
• Current - Supply: 11.7mA
• Current - Output / Channel: 16mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SMD Gull Wing
• Operating Supply Voltage (typ): 5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

Figure 17. Recommended HCPL-7520 application circuit.
As shown in Figure 17, 0.1 µF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
HCPL-7520. The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
HCPL-7520. A 0.01 µF bypass capacitor (C2) is also rec-
ommended at the input due to the switched-capacitor
nature of the input circuit. The input bypass capacitor
also forms part of the anti-aliasing filter, which is recom-
mended to prevent high frequency noise from aliasing
down to lower frequencies and interfering with the
input signal. The input filter also performs an important
reliability function—it reduces transient spikes from ESD
events flowing through the current sensing resistor.
12
MOTOR
R
+
SENSE
R1
-
HV+
HV-
0.1 µF
C1
IN
GATE DRIVE
FLOATING
POSITIVE
78L05
SUPPLY
CIRCUIT
U1
OUT
68 Ω
R5
0.1 µF
C2
0.01 µF
C3
PC Board Layout
The design of the printed circuit board (PCB) should
follow good layout practices, such as keeping bypass
capacitors close to the supply pins, keeping output
signals away from input signals, the use of ground and
power planes, etc. In addition, the layout of the PCB
can also affect the isolation transient immunity (CMTI)
of the HCPL-7520, due primarily to stray capacitive
coupling between the input and the output circuits. To
obtain optimal CMTI performance, the layout of the PC
board should minimize any stray coupling by maintain-
ing the maximum possible distance between the input
and output sides of the circuit and ensuring that any
ground or power plane on the PC board does not pass
directly below or extend much wider than the body of
the HCPL-7520.
1
2
3
4
V
V
V
GND1
DD1
IN+
IN-
HCPL-7520
GND2
V
V
V
OUT
DD2
REF
8
7
6
5
+5 V
C4
C6 = 150 pF
C4 = C5 = 0.1 µF
C5
C6
A/D
V
GND
REF
µC