HCPL-316J-500E Avago Technologies US Inc., HCPL-316J-500E Datasheet

OPTOCOUPLER 2CH 2.5A 16-SOIC

HCPL-316J-500E

Manufacturer Part Number
HCPL-316J-500E
Description
OPTOCOUPLER 2CH 2.5A 16-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HCPL-316J-500E

Configuration
High-Side
Package / Case
16-SOIC (0.300", 7.5mm Width)
Input Type
Differential
Delay Time
300ns
Current - Peak
2.5A
Number Of Configurations
1
Number Of Outputs
1
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Fall Time
0.1 us
Rise Time
0.1 us
Isolation Voltage
3750 Vrms
Maximum Power Dissipation
1200 mW
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
516-1777-2
HCPL-316J-500E

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HCPL-316J-500E
Manufacturer:
AVAGO
Quantity:
3 200
Part Number:
HCPL-316J-500E
Quantity:
20 400
Part Number:
HCPL-316J-500E
Manufacturer:
AGILENT
Quantity:
17
Part Number:
HCPL-316J-500E
Manufacturer:
ST
0
HCPL-316J
2.5 Amp Gate Drive Optocoupler with Integrated (V
Desaturation Detection and Fault Status Feedback
Data Sheet
Description
Avago’s 2.5 Amp Gate Drive Optocoupler with Integrated
Desaturation (V
makes IGBT V
easy-to-implement while satisfying worldwide safety and
regulatory requirements.
Features
x 2.5 A maximum peak output current
x Drive IGBTs up to I
x Optically isolated, FAULT status feedback
x SO-16 package
x CMOS/TTL compatible
x 500 ns max. switching speeds
Fault Protected IGBT Gate Drive
3-PHASE
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
INPUT
Lead (Pb) Free
RoHS 6 fully
compliant
CE
fault protection compact, affordable, and
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
CE
–HV
+HV
) Detection and Fault Status Feedback
C
= 150 A, V
HCPL - 316J
BOUNDARY
ISOLATION
CE
= 1200V
FAULT
BOUNDARY
HCPL - 316J
ISOLATION
HCPL - 316J
BOUNDARY
ISOLATION
MICRO-CONTROLLER
Features (continued)
x “Soft” IGBT turn-off
x Integrated fail-safe IGBT protection
x User configurable: inverting, noninverting, auto-reset,
x Wide operating V
x -40°C to +100°C operating temperature range
x 15 kV/μs min. Common Mode Rejection (CMR) at
x Regulatory approvals: UL, CSA, IEC/EN/DIN EN 60747-
CE
– Desat (V
– Under Voltage Lock-Out protection (UVLO)
with hysteresis
auto-shutdown
V
5-2 (1230V
)
BOUNDARY
HCPL - 316J
ISOLATION
CM
HCPL - 316J
= 1500V
BOUNDARY
ISOLATION
CE
peak
) detection
Working Voltage)
CC
range: 15 to 30 Volts
BOUNDARY
HCPL - 316J
ISOLATION
HCPL - 316J
BOUNDARY
ISOLATION
M

Related parts for HCPL-316J-500E

HCPL-316J-500E Summary of contents

Page 1

... Common Mode Rejection (CMR 1500V CM x Regulatory approvals: UL, CSA, IEC/EN/DIN EN 60747- 5-2 (1230V ISOLATION ISOLATION BOUNDARY BOUNDARY HCPL - 316J HCPL - 316J HCPL - 316J HCPL - 316J ISOLATION ISOLATION BOUNDARY BOUNDARY FAULT MICRO-CONTROLLER ) detection CE range Volts CC Working Voltage) peak ISOLATION ...

Page 2

... V IN- UVLO is not active (V go high, and the DESAT (pin 14) detection feature of the HCPL-316J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V > 11.6 V, DESAT will remain functional until V VLO+ 12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection ...

Page 3

... During power-up, the Under Voltage Lockout (UVLO) fea- ture prevents the application of insufficient gate voltage to the IGBT, by forcing the HCPL-316J’s output low. Once the output is in the high state, the DESAT (V tion feature of the HCPL-316J provides IGBT protection. ...

Page 4

... V. FAULT output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all HCPL-316Js in a circuit to be connected together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller. ...

Page 5

... To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-316J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-316J to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and non RoHS compliant ...

Page 6

Package Characteristics All specifications and figures are at the nominal (typical) operating conditions and T = +25° Parameter Input-Output Momentary Withstand Voltage Resistance (Input-Output) Capacitance (Input-Output) Output IC-to-Pins 9 ...

Page 7

... Regulatory Information The HCPL-316J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-5:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ ...

Page 8

Insulation and Safety Related Specifications Parameter Symbol Minimum External Air Gap L(101) (Clearance) Minimum External Tracking L(102) (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance CTI (Comparative Tracking Index) Isolation Group Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature ...

Page 9

Electrical Specifications (DC) Unless otherwise noted, all typical values at T all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Logic Low Input Voltages IN+L V RESETL Logic High Input Voltages IN+H V ...

Page 10

Switching Specifications (AC) Unless otherwise noted, all typical values at T all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter V to High Level Output IN Propagation Delay Time V to Low Level Output IN Propagation Delay Time Pulse Width ...

Page 11

... This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaran- teed minimum FAULT signal pulse width when the HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the end of this data sheet for further details. ...

Page 12

Performance Plots 2.0 1.8 1.6 1.4 1.2 1.0 -40 - 100 T – TEMPERATURE – °C A Figure 3. I vs. temperature -650 μA OUT I = -100 mA OUT -1 ...

Page 13

I CC2H I CC2L 2.40 2. – OUTPUT SUPPLY VOLTAGE – V CC2 Figure 12 CC2 CC2 -40°C +25°C 1 +100° 0.5 ...

Page 14

PLH t PHL 0.35 0.30 0.25 0. 100 LOAD CAPACITANCE – nF Figure 21. Propagation delay vs. load capaci- tance. 3 CC2 CC2 2.5 2.0 ...

Page 15

Test Circuit Diagrams V IN+ 0.1 μ IN- 4.5 V – V CC1 GND1 – 0 RESET FAULT I FAULT V LED1+ V LED1- Figure 30. I test circuit. FAULTL V V IN+ 0.1 μF 5 ...

Page 16

V IN+ 0.1 μ IN – V CC1 GND1 RESET FAULT V LED1+ V LED1- Figure 36. V test circuit IN+ 0.1 V IN- μF 5 – V CC1 I CC1 ...

Page 17

– IN- LED2 DSCHG V DESAT CC1 GND1 V CC2 RESET V C FAULT V OUT V V LED1 LED1- EE Figure 42. I test circuit. DSCHG ...

Page 18

V IN+ 0.1 μ IN- – CC1 GND1 V HIGH LOW RESET V FAULT FAULT V LED1+ V LED1- Figure 48. t test circuit. RESET(FAULT IN ...

Page 19

IN- V 2.5 V 2 OUT t t PLH PHL Figure 54. V propagation delay waveforms, noninverting configuration. OUT t DESAT (FAULT) t DESAT (10%) t DESAT (LOW ...

Page 20

V V IN+ 0.1 μ IN- LED2+ – V DESAT CC1 GND1 V CC2 RESET V FAULT V OUT V V LED1 LED1- EE Figure 57. I test circuit ...

Page 21

... The fault detection method, which is adopted in the HCPL-316J monitor the saturation (collector) volt- age of the IGBT and to trigger a local fault shutdown se- quence if the collector voltage exceeds a predetermined threshold ...

Page 22

... Figure 62. Recommended application circuit. Description of Operation/Timing Figure 63 below illustrates input and output waveforms under the conditions of normal operation, a desat fault condition, and normal reset behavior. Normal Operation During normal operation the HCPL-316J is con- OUT trolled by either with the IGBT collector-to- IN+ IN- ...

Page 23

... Under Voltage Lockout The HCPL-316J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the HCPL-316J output low during power-up. IGBTs typically require gate voltages achieve their rated V voltages below 13 V typically, their on-voltage increases dramatically, especially at higher currents ...

Page 24

... Behavioral Circuit Schematic The functional behavior of the HCPL-316J is rep- resented by the logic diagram in Figure 64 which fully describes the interaction and se- quence of internal and external signals in the HCPL-316J. Input IC In the normal switching mode, no output fault has been detected, and the low state of the fault latch allows the input signals to control the signal LED ...

Page 25

... IN- switching of the output under extreme common mode transient conditions. Input drive circuits that use pull-up or pull-down resistors, such as open collector configu- rations, should be avoided. Standard CMOS or TTL drive circuits are recommended. HCPL-316J IN- ...

Page 26

... V is held high by connecting IN+ gled. Local Shutdown, Local Reset As shown in Figure 70, the fault output of each HCPL- 316J gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. Global-Shutdown, Global Reset As shown in Figure 71, when configured for inverting op- ...

Page 27

... Auto-Reset As shown in Figure 72, when the inverting V connected to ground (non-inverting configuration), the HCPL-316J can be configured to reset automatically by connecting RESET this case, the gate control IN+ signal is applied to the non-inverting input as well as the reset input to reset the fault latch every switching cycle. During normal operation of the IGBT, asserting the reset input low has no effect ...

Page 28

... User-Configuration of the HCPL-316J Output Side R and Optional Resistor The value of the gate resistor R (along with V G determines the maximum amount of gate-charging/dis- charging current (I and I ON,PEAK OFF,PEAK be carefully chosen to match the size of the IGBT being driven. Often it is desirable to have the peak gate charge ...

Page 29

... Value When choosing the value important to con- G firm that the power dissipation of the HCPL-316J is within the maximum allowable power rating. The steps for doing this are: 1. Calculate the minimum desired R 29 DESAT Diode and DESAT Threshold The DESAT diode’s function is to conduct forward cur- rent, allowing sensing of the IGBT’ ...

Page 30

... HCPL-316J for a given PC board layout configuration. SWITCH SWITCHING ENERGY v . GATE RESISTANCE Figure 77. Switching energy plot for calculating average Pswitch (for HCPL-316J output driving an IGBT rated at 600 V/100 A). = transient power dissipation in the HC- CC1 and I CC1H CC1L = 5.5 mA. CC2 + P O,SWITCH ( CC2 EE2 E ...

Page 31

... Thermal Model The HCPL-316J is designed to dissipate the majority of the heat through pins 4 for the input IC and pins 9 and 10 for the output IC. (There are two V EE side, pins 9 and 10, for this purpose.) Heat flow through other pins or through the package directly into ambient are considered negligible and not modeled here ...

Page 32

... Ground Plane connections are necessary for pin 4 (GND1) and pins 9 and order to achieve maximum EE power dissipation as the HCPL-316J is designed to dissi- pate the majority of heat generated through these pins. Actual power dissipation will depend on the application environment (PCB layout, air flow, part placement, etc.) See the Thermal Model section for details on how to es- timate junction temperature ...

Page 33

... Figure 81. The maximum dead time for the HCPL-316J is 800 ns (= 400 ns - (-400 ns)) over an operat- ing temperature range of -40°C to 100°C. Note that the propagation delays used to calculate PDD ...

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