X40431S14-A Intersil, X40431S14-A Datasheet - Page 7

• Manufacturer Part Number: X40431S14-A
• Description: IC VOLT MON TRPL EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40431S14-A

• Number Of Voltages Monitored: 3
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.7V, 2.9V, 4.6V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PRINCIPLES OF OPERATION
Power-on Reset
Applying power to the X40430, X40431, X40434,
X40435 activates a Power-on Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for t
(X40431, X40435) and RESET (X40430, X40434) pin
allowing the system to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
Manual Reset
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The
MR pin is LOW while the push-button is closed and
RESET/RESET pin remains HIGH/LOW until the push-
button is released and for t
Low Voltage V
During operation, the X40430, X40431, X40434,
X40435
RESET/RESET if supply voltage falls below a preset
minimum V
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains
active until V
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
RESET to prevent the microprocessor from operating
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
PURST
System
Reset
TRIP2
CC
monitors
(selectable) the circuit releases the RESET
exceeds the device V
TRIP1
CC
. The V2FAIL signal is either ORed with
CC
returns and exceeds V
. The RESET/RESET signal prevents
X40430, X40434
RESET
(V1 Monitoring)
the
MR
PURST
7
V
CC
thereafter.
TRIP1
level
V
CC
X40430, X40431, X40434, X40435
TRIP1
threshold value
and
for
Manual
Reset
t
PURST
asserts
.
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
For the X40430 and X40431 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON falling). It also remains active until V2MON
returns and exceeds V
cuitry monitors the power supply connected to V2MON
pin. If V
For the X40434 and X40435, the V2FAIL signal
remains active until V
active until V2MON returns and exceeds V
sense circuitry is powered by V
cannot be monitored.
Low Voltage V3 Monitoring
The X40430, X40431, X40434, X40435 also monitors
a third voltage level and asserts V3FAIL if the voltage
falls below a preset minimum V
nal is either ORed with RESET to prevent the micro-
processor from operating in a power fail or brownout
condition or used to interrupt the microprocessor with
notification of an impending power failure. The V3FAIL
signal remains active until the V3MON drops below 1V
(V3MON falling). It also remains active until V3MON
returns and exceeds V
This voltage sense circuitry monitors the power supply
connected to V3MON pin. If V
be monitored.
Early Low V
This
RESET/RESET whenever V
voltage and returns high when V
V
(t
TRIP1
PURST
CMOS
CC
) on this pin.
voltage. There is no power-up delay circuitry
= 0, V2MON can still be monitored.
CC
Detection (LOWLINE)
output
CC
TRIP3
TRIP2
drops below 1V and remains
goes
.
CC
. This voltage sense cir-
CC
CC
TRIP3
falls below the V
LOW
= 0, V3MON can still
. If V
. The V3FAIL sig-
CC
CC
earlier
exceeds the
= 0, V2MON
TRIP2
May 24, 2006
FN8251.1
. This
TRIP1
than