X40626V14 Intersil, X40626V14 Datasheet - Page 11

• Manufacturer Part Number: X40626V14
• Description: IC SUPERVISOR CPU DUAL 14-TSSOP
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40626V14

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 2.93V, 4.38V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 11. Acknowledge Polling Sequence
Figure 12. Current Address Read Sequence
Command Sequence
command sequence?
Issue Slave Address
Byte (Read or Write)
Byte load completed
complete. Continue
Enter ACK Polling
by issuing STOP.
Nonvolatile Cycle
Continue Normal
Read or Write
Issue START
PROCEED
returned?
ACK
YES
YES
11
Signals from
Signals from
the Master
the Slave
NO
SDA Bus
NO
Issue STOP
Issue STOP
S
a
t
r
t
1 0 1 0 0
Address
Slave
X40626
S
1
S
0
1
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address in the
address counter is 00H.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 12 for the
address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
A
C
K
Data
S
o
p
t
March 28, 2005
FN8119.0