X5328V14I Intersil, X5328V14I Datasheet - Page 4
![IC SUPERVISOR CPU 32K EE 14TSSOP](/photos/6/58/65830/20-14-tssop_sml.jpg)
X5328V14I
Manufacturer Part Number
X5328V14I
Description
IC SUPERVISOR CPU 32K EE 14TSSOP
Manufacturer
Intersil
Type
Simple Reset/Power-On Resetr
Datasheet
1.X5328PZ.pdf
(21 pages)
Specifications of X5328V14I
Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
100 ms Minimum
Voltage - Threshold
4.38V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PIN DESCRIPTION
PIN CONFIGURATION
(SOIC/PDIP)
Pin
1
2
5
6
3
4
8
7
V
CS
SO
WP
CC
3-5,10-12
TSSOP
Pin
14
13
1
2
8
9
6
7
1
2
3
4
8 Ld SOIC/PDIP
X5328/29
4
RESET/
RESET
Name
SCK
V
V
WP
SO
NC
CS
SI
CC
SS
8
7
6
5
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V
will remain active until V
RESET/RESET goes active on power-up at about 1V and remains active for
200ms after the power supply stabilizes.
No internal connections
V
RESET/RESET
SCK
SI
CC
X5328, X5329
CC
rises above the minimum V
V
WP
SO
NC
NC
NC
CS
SS
CC
falls below the minimum V
Function
14 Ld TSSOP
1
2
3
4
5
6
7
X5328/29
14
13
12
11
10
9
8
CC
V
NC
NC
NC
RESET/RESET
SCK
SI
CC
sense level for 200ms.
CC
sense level. It
October 17, 2005
FN8132.1