LP38852MR-ADJ/NOPB National Semiconductor, LP38852MR-ADJ/NOPB Datasheet - Page 12

• Manufacturer Part Number: LP38852MR-ADJ/NOPB
• Description: IC REG LDO 1.5A LOW I/O 8-PSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP38852MR-ADJ/NOPB

• Regulator Topology: Positive Adjustable
• Voltage - Output: 0.8 ~ 1.8 V
• Voltage - Input: 0.93 ~ 5.5 V
• Voltage - Dropout (typical): 0.13V @ 1.5A
• Number Of Regulators: 1
• Current - Output: 1.5A (Max)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-PSOP
• For Use With: LP38852EVAL - BOARD EVALUATION LP38852
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Other names: LP38852MR-ADJ

www.national.com
Please refer to Application Note AN-1378 for additional infor-
mation on how resistor tolerances affect the calculated V
value.
INPUT VOLTAGE
The input voltage (V
that will be regulated down to a lower voltage, which is applied
to the load. The input voltage must be at least V
and no higher than whatever value is used for V
BIAS VOLTAGE
The bias voltage (V
required to bias the control circuitry and provide gate drive for
the N-FET pass transistor. When V
V
If V
and 5.5V to ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
device from functioning when the bias voltage is below the
Under-Voltage Lock-Out (UVLO) threshold of approximately
2.45V.
As the bias voltage rises above the UVLO threshold the de-
vice control circuitry becomes active. There is approximately
150 mV of hysteresis built into the UVLO threshold to provide
noise immunity.
When the bias voltage is between the UVLO threshold and
the Minimum Operating Rating value of 3.0V the device will
be functional, but the operating parameters will not be within
the guaranteed limits.
SUPPLY SEQUENCING
There is no requirement for the order that V
applied or removed.
One practical limitation is that the Soft-Start circuit starts
charging C
old and the Enable pin is above the V
application of V
Soft-Start will be compromised.
In any case, the output voltage cannot be guaranteed until
both V
ating values.
If used in a dual-supply system where the regulator output
load is returned to a negative supply, the output pin must be
diode clamped to ground. A Schottky diode is recommended
for this diode clamp.
BIAS
OUT
V
0.8V
0.9V
1.0V
1.1V
1.2V
1.3V
1.4V
1.5V
1.6V
1.7V
1.8V
OUT
may be anywhere in the operating range of 3.0V to 5.5V.
IN
is set higher than 1.20V , V
and V
SS
when both V
1.07 kΩ
1.50 kΩ
1.00 kΩ
1.65 kΩ
1.40 kΩ
1.15 kΩ
1.07 kΩ
2.00 kΩ
1.65 kΩ
2.55 kΩ
2.94 kΩ
BIAS
IN
R1
is delayed beyond this point the benefits of
are within the range of guaranteed oper-
BIAS
IN
) is the high current external voltage rail
) is a low current external voltage rail
TABLE 1.
1.78 kΩ
1.87 kΩ
1.00 kΩ
1.37 kΩ
1.00 kΩ
1.00 kΩ
1.07 kΩ
1.13 kΩ
715 Ω
590 Ω
750 Ω
BIAS
R2
rises above the UVLO thresh-
BIAS
OUT
8.2 nF
8.2 nF
6.8 nF
8.2 nF
5.6 nF
4.7 nF
must be between 4.5V
EN(ON)
is set to 1.20V, or less,
12 nF
12 nF
10 nF
12 nF
12 nF
C
FF
threshold. If the
IN
BIAS
or V
12.4 kHz
12.9 kHz
13.3 kHz
11.8 kHz
11.4 kHz
11.5 kHz
12.4 kHz
11.7 kHz
11.8 kHz
11.1 kHz
11.5 kHz
OUT
.
BIAS
F
+ V
Z
OUT
are
DO
,
12
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the
output pin is higher than the voltage at the input pin. Typically
this will happen when V
tinues to hold a sufficient charge such that the input to output
voltage becomes reversed.
The NMOS pass element, by design, contains no body diode.
This means that, as long as the gate of the pass element is
not driven, there will not be any reverse current flow through
the pass element during a reverse voltage event. The gate of
the pass element is not driven when V
threshold, or when the Enable pin is held low.
When V
is above the V
and will attempt to regulate the output voltage. Since the input
voltage is less than the output voltage the control circuit will
drive the gate of the pass element to the full V
when the output voltage begins to fall. In this condition, re-
verse current will flow from the output pin to the input pin ,
limited only by the R
to input voltage differential. Discharging an output capacitor
up 1000 µF in this manner will not damage the device as the
current will rapidly decay. However, continuous reverse cur-
rent should be avoided.
SOFT-START
The LP38852 incorporates a Soft-Start function that reduces
the start-up current surge into the output capacitor (C
allowing V
plished by controlling V
capacitor (C
rises above the Under-Voltage Lock-Out threshold (ULVO)
and the Enable pin is higher than the V
V
of the SS pin (r
the SS pin. This allows the output voltage to rise in a con-
trolled manner until steady-state regulation is achieved. Typ-
ically, five time constants are recommended to assure that the
output voltage is sufficiently close to the final steady-state
value. During the soft-start time the output current can rise to
the built-in current limit.
Since the V
current will peak during the first time constant (τ), and V
will require four additional time constants (4τ) to reach the final
value (5τ) .
After achieving normal operation, should either V
low the ULVO threshold, or the Enable pin fall below the V
(OFF)
Start capacitor (C
C
mV (typical). When V
C
sufficient biasing to the control circuitry.
Since V
will cause V
nA (about 10 MΩ) through C
imately 0.1% lower than nominal, while a leakage of 500 nA
(about 1 MΩ) will cause V
than nominal. Typical ceramic capacitors will have a factor of
10X difference in leakage between 25°C and 85°C, so the
maximum ambient temperature must be included in the ca-
pacitor selection process.
REF
SS
SS
discharge circuit will remain active until V
discharge circuit will cease to function due to a lack of
threshold, the device output will be disabled and the Soft-
will rise at an RC rate defined by the internal resistance
REF
BIAS
OUT
OUT
Soft-Start Time = C
appears on the SS pin, any leakage through C
REF
is above the UVLO threshold, and the Enable pin
SS
to rise slowly to the final value. This is accom-
EN(ON)
) is internally held to ground until both V
rise will be exponential, not linear, the in-rush
SS
to fall, and thus affect V
SS
), and the external capacitor connected to
) discharge circuit will become active. The
DS(ON)
threshold, the control circuitry is active
BIAS
REF
IN
is abruptly taken low and C
of the pass element and the output
OUT
at the SS pin. The soft-start timing
falls below 500 mV (typical), the
SS
to be approximately 1% lower
SS
will cause V
× r
SS
BIAS
EN(ON)
× 5
OUT
is below the UVLO
OUT
. A leakage of 50
BIAS
threshold.
to be approx-
BIAS
BIAS
falls to 500
potential
OUT
OUT
fall be-
con-
) by
BIAS
OUT
(7)
EN
SS