NCV4299D233R2G ON Semiconductor, NCV4299D233R2G Datasheet - Page 16

• Manufacturer Part Number: NCV4299D233R2G
• Description: IC REG LDO 150MA 3.3V 14-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCV4299D233R2G

• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V
• Voltage - Input: 4.4 ~ 45 V
• Voltage - Dropout (typical): 0.22V @ 100mA
• Number Of Regulators: 1
• Current - Output: 150mA
• Current - Limit (min): 250mA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 45 V
• Output Voltage: 3.3 V
• Output Type: Fixed
• Dropout Voltage (max): 0.5 V at 100 mA
• Output Current: 150 mA
• Line Regulation: 25 mV
• Load Regulation: 30 mV
• Voltage Regulation Accuracy: 2 %
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCV4299D233R2G; NCV4299D233R2GOSTR

Reset Output (RO)
generated as the IC powers up. After the output voltage V
increases above the reset threshold voltage V
timer D is started. When the voltage on the delay timer V
passes V
the delay timer (V
below the reset threshold voltage V
Reset Adjust (RADJ)
value of 4.64 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figures 39 and 40. The resistor divider keeps the
voltage above the V
input voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.64 V).
A reset signal, Reset Output (RO, low voltage) is
The reset threshold V
If the reset adjust option is not needed, the RADJ−pin
V THRES + V RADJ, TH · (R ADJ1 ) R ADJ2 ) R ADJ2
V
RO,SAT
V
V
UD
V
UD
RT
LD
V
V
V
RO
, the reset signal RO goes high. A discharge of
Power−on−Reset
V
Q
D
I
D
t
d
RADJ,TH
) is started when V
RT
can be decreased from a typical
, (typ. 1.36 V), for the desired
Shutdown
Thermal
RT
. When the voltage of
t
RR
Q
drops and stays
Figure 41. Reset Timing Diagram
RT
, the delay
Voltage Dip
at Input
http://onsemi.com
(eq. 1)
Q
D
16
Undervoltage
the delay timer (V
voltage V
reset the processor.
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for V
Reset Delay (D)
capacitor C
provides charge current I
delay capacitor C
The reset output RO is an open collector NPN transistor,
The reset delay circuit provides a delay (programmable by
1. During Powerup (once the regulation threshold has
2. After a reset event has occurred and the device
been exceeded).
is back in regulation. The delay capacitor is
set to discharge when the regulation (V
threshold voltage) has been violated. When
the delay capacitor discharges to down to V
the reset signal RO pulls low.
LD
D
, the reset output voltage V
) on the reset output RO lead. The delay lead D
Secondary
D
Spike
during the following times:
D
) drops below the lower threshold
D
< t
(typically 7.1 mA) to the external
RR
Overload
at Output
dV
dt
Q
+
as low as 1.0 V.
C D
I D
RO
is brought low to
RT
, reset
t
t
t
t
LD
,