NCV4299D233R2G ON Semiconductor, NCV4299D233R2G Datasheet - Page 17

• Manufacturer Part Number: NCV4299D233R2G
• Description: IC REG LDO 150MA 3.3V 14-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCV4299D233R2G

• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V
• Voltage - Input: 4.4 ~ 45 V
• Voltage - Dropout (typical): 0.22V @ 100mA
• Number Of Regulators: 1
• Current - Output: 150mA
• Current - Limit (min): 250mA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 45 V
• Output Voltage: 3.3 V
• Output Type: Fixed
• Dropout Voltage (max): 0.5 V at 100 mA
• Output Current: 150 mA
• Line Regulation: 25 mV
• Load Regulation: 30 mV
• Voltage Regulation Accuracy: 2 %
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCV4299D233R2G; NCV4299D233R2GOSTR

Setting the Delay Time
charge current I
capacitor voltage charging from the low level of V
higher level V
Example:
Using C
Use the typical value for V
Use the typical value for V
Use the typical value for Delay Charge Current I
threshold voltage V
starts to drop. The time it takes to drop below the lower
threshold voltage of V
time is typically 2.2 ms for a delay capacitor of 0.1 mF. The
reset reaction time can be estimated from the following
relationship:
Calculating Power Dissipation in a Single Output
Linear Regulator
regulator is:
where:
V
V
I
and
Q(max)
I(max)
Q(min)
The delay time is set by the delay capacitor C
When the output voltage V
The maximum power dissipation for a single output
P D(max) + [V I(max) −V Q(min) ] I Q(max) ) V I(max) Iq
V
SI,Low
t d + [100 nF(1.85−0.1 V)] 7.1 mA + 24.6 ms
V
V
V
V
RO
SO
Figure 42. SO Warning Timing Waveform
SI
Q
is the maximum output current for the application,
is the maximum input voltage,
D
is the minimum output voltage,
= 100 nF.
UD
t d + [C D (V UD −V D, sat )] I D
T
WARNING
D
. The time delay follows the equation:
t RR + 22 ns nF
. The time is measured by the delay
RT
, the voltage on the delay capacitor V
LD
is the reset reaction time, t
D,sat
UD
= 1.85 V.
= 0.1 V.
Q
drops below the reset
C D
D
D,sat
D
= 7.1 mA.
RR
and the
http://onsemi.com
(eq. 2)
(eq. 3)
(eq. 4)
(eq. 5)
. This
to the
D
Voltage
Output
17
Sense
Sense
V
V
Input
SI,High
SI,Low
High
Low
Sense Input (SI)/Sense Output (SO) Voltage Monitor
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (SI) (Figures 39 and 40). The
typical threshold is 1.35 V on the SI Pin.
Signal Output
the circuits depicted in Figures 39 and 40. As the output
voltage V
This causes the voltage on the SO output to go low sending
a warning signal to the microprocessor that a reset signal may
occur in a short period of time. T
microprocessor has to complete the function it is currently
working on and get ready for the reset shutdown signal.
I
permissible value of R
package section of the data sheet. Those packages with
R
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required.
q
qJA
An on−chip comparator is available to provide early
Figure 42 shows the SO Monitor waveforms as a result of
Once the value of P
The value of R
is the quiescent current the regulator consumes at I
’s less than the calculated value in Equation 6 will keep
Figure 43. Sense Timing Diagram
Q
falls, the monitor threshold V
R qJA + (150° C−T A ) P D
qJA
can then be compared with those in the
qJA
t
PSOLH
D(max)
can be calculated:
is known, the maximum
WARNING
SI,Low
is the time the
is crossed.
t
PSOHL
Q(max)
(eq. 6)
t
t
.