FDMA507PZ Fairchild Semiconductor, FDMA507PZ Datasheet - Page 2

• Manufacturer Part Number: FDMA507PZ
• Description: MOSFET P-CH 20V 6-MICROFET
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDMA507PZ

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 24 mOhm @ 7.8A, 5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 7.8A
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 42nC @ 5V
• Input Capacitance (ciss) @ Vds: 2015pF @ 10V
• Power - Max: 900mW
• Mounting Type: Surface Mount
• Package / Case: *
• Configuration: Single
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 45 mOhms
• Forward Transconductance Gfs (max / Min): 33 S
• Drain-source Breakdown Voltage: - 20 V
• Continuous Drain Current: - 7.8 A
• Power Dissipation: 2.4 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Gate Charge Qg: 30 nC
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDMA507PZTR

©2010 Fairchild Semiconductor Corporation
FDMA507PZ Rev.C
Electrical Characteristics
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Notes:
1. R
2. Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
BV
∆BV
I
I
V
r
g
C
C
C
t
t
t
t
Q
Q
Q
V
t
Q
∆V
DSS
GSS
d(on)
r
d(off)
f
rr
DS(on)
FS
GS(th)
SD
the user's board design.
iss
oss
rss
∆T
∆T
g(TOT)
gs
gd
rr
Symbol
θJA
DSS
GS(th)
DSS
J
J
is determined with the device mounted on a 1 in
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Parameter
2
T
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
J
a. 52 °C/W when mounted on
= 25 °C unless otherwise noted
a 1 in
2
pad of 2 oz copper.
I
I
V
V
V
I
V
V
V
V
V
V
V
f = 1 MHz
V
V
V
V
V
I
D
D
D
F
DS
GS
GS
GS
GS
GS
GS
GS
DS
DS
DD
GS
DD
GS
GS
= -250 µA, V
= -250 µA, referenced to 25 °C
= -250 µA, referenced to 25 °C
= -7.8 A, di/dt = 100 A/µs
= -16 V, V
= -5 V, I
= -10 V, V
= -5 V
= ±8 V, V
= V
= -5 V, I
= -4.5 V, I
= -2.5 V, I
= -1.8 V, I
= -5 V, I
= -10 V, I
= -5 V, R
= -10 V, I
= 0 V, I
DS
2
Test Conditions
, I
S
D
D
D
D
GEN
D
= -2.0 A
DS
D
GS
= -7.8 A
= -7.8 A, T
= -7.8 A
GS
= -250 µA
GS
D
D
D
= -7.8 A
= -7.8 A
= 0 V
= -7 A
= -5.5 A
= -4 A
= 0 V,
= 0 V
= 6 Ω
= 0 V
(Note 2)
J
= 125 °C
θJC
is guaranteed by design while R
-0.4
Min
-20
b. 145 °C/W when mounted on a
minimum pad of 2 oz copper.
1515
265
240
-0.6
192
-0.5
6.4
7.5
Typ
66
44
14
96
30
-12
19
20
24
29
26
33
2
3
2015
θCA
-1.2
Max
355
360
307
154
106
-1.5
±10
13
25
42
70
24
25
35
45
34
www.fairchildsemi.com
-1
is determined by
mV/°C
mV/°C
Units
mΩ
nC
pF
pF
pF
nC
nC
nC
µA
µA
ns
ns
ns
ns
ns
V
V
V
S