AK5392VSP AKM Semiconductor Inc, AK5392VSP Datasheet

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AK5392VSP

Manufacturer Part Number
AK5392VSP
Description
IC ADC DGTL AUDIO 24BIT 28SOP
Manufacturer
AKM Semiconductor Inc
Type
ADCr
Datasheet

Specifications of AK5392VSP

Resolution (bits)
24 b
Sampling Rate (per Second)
1k ~ 54k
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3.3V, 5V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
974-1036-2
AK5392VSP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AK5392VSP-E2
Manufacturer:
AKM
Quantity:
928
ASAHI KASEI
The AK5392 is a 24bit, 128x oversampling 2ch A/D Converterfor professional digital audio systems. The modulator
in the AK5392 uses the new developed Enhanced Dual Bit architecture. This new architecture achieves the wider
dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. The
AK5392 performs 116dB dynamic range, so the device is suitable for professional studio equipments such as digital
mixer, digital VTR etc.
0188-E-01
Enhanced Dual Bit ADC
Sampling Rate: 1kHz 54kHz
Full Differential Inputs
S/(N+D): 105dB
DR: 116dB
S/N: 116dB
High Performance Linear Phase Digital Anti-Alias filter
Digital HPF & Offset Calibration for Offset Cancel
Master Clock: 256/384fs
Power Supply: 5V±5%(Analog), 3 5.25V(Digital)
Power Dissipation: 470mW
Package: 28pin SOP
Passband: 0 21.768kHz(@fs=48kHz)
Ripple: 0.001dB
Stopband: 110dB
General Description
Features
- 1 -
Enhanced Dual Bit
AK5392
24Bit ADC
[AK5392]
1997/11

Related parts for AK5392VSP

AK5392VSP Summary of contents

Page 1

ASAHI KASEI The AK5392 is a 24bit, 128x oversampling 2ch A/D Converterfor professional digital audio systems. The modulator in the AK5392 uses the new developed Enhanced Dual Bit architecture. This new architecture achieves the wider dynamic range, while keeping much ...

Page 2

ASAHI KASEI Ordering Guide AK5392-VS AKD5392 Pin Layout Compatibility with AK5391 1. Changed Specs Parameter HPF Output Resolution DR Input Offset 2. Pin Compatibility The following pin functions are changed from AK5391. AK5392 supports 24bit only. Pin No. AK5391 2 ...

Page 3

ASAHI KASEI No. Pin Name I/O 1 VREFL O Lch Reference Voltage Pin, 3.75V Normally connected to GNDL with a 10uF electrolytic capacitor and a 0.1uF ceramic capacitor 2 GNDL - Lch Reference Ground Pin VCOML O Lch ...

Page 4

ASAHI KASEI 14 SCLK I/O Serial Data Clock Pin Data is clocked out on the falling edge of SCLK. Slave mode: Master mode: 15 SDATA O Serial Data Output Pin MSB first, 2's complement. SDATA stays "L" during reset. 16 ...

Page 5

ASAHI KASEI (AGND,BGND,DGND=0V; Note 1 ) Parameter Power Supplies: Analog Digital |BGND-DGND| (Note 2 ) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Note All voltages with respect ...

Page 6

ASAHI KASEI C (Ta=25 ; VA=5.0V; VD=3.3V; AGND,BGND,DGND=0V; fs=48kHz; Signal Frequency=1kHz; 24bit Output; Measurement frequency=10Hz 20kHz; unless otherwise specified) Parameter Resolution Analog Input Characteristics: S/(N+D) (Note 4 ) -1dBFS -20dBFS -60dBFS S/N (A-Weighted) Dynamic Range (A-Weighted,-60dBFS) Interchannel Isolation Interchannel Gain ...

Page 7

ASAHI KASEI C (Ta=25 ; VA=5.0V±5%; VD=3.0 5.25V; fs=48kHz) Parameter ADC Digital Filter(Decimation LPF): Passband (Note 6 ) Stopband (Note 6 ) Passband Ripple Stopband Attenuation (Note 7 ) Group Delay Distortion Group Delay (Note 8 ) ADC Digital Filter(HPF): ...

Page 8

ASAHI KASEI (Ta= VA=5.0V±5%; VD=3.0 5.25V; CL=20pF) Parameter Control Clock Frequency Master Clock 256fs: Pulse width Low Pulse width High 384fs: Pulse width Low Pulse width High Serial Data Output Clock (SCLK) Channel Select Clock (LRCK) duty cycle ...

Page 9

ASAHI KASEI Timing Diagram 0188-E- [AK5392] 1997/11 ...

Page 10

ASAHI KASEI 0188-E- [AK5392] 1997/11 ...

Page 11

ASAHI KASEI System Clock Input The external clocks which are required to operate the AK5392 are MCLK, LRCK(fs),SCLK. MCLK should be synchronized with LRCK but the phase is free of care. MCLK can be either 256fs or 384fs by setting ...

Page 12

ASAHI KASEI 0188-E- [AK5392] 1997/11 ...

Page 13

ASAHI KASEI Offset Calibration RST When pin goes to "L", the digital section is powered-down. Upon returning "H", an offset calibration cycle is started. An offset calibration cycle should always be initiated after power-up. During the offset calibration cycle, the ...

Page 14

ASAHI KASEI Figure 5 shows the system connection diagram. An evaluation board[AKD5392] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 0188-E-01 SYSTEM DESIGN Figure 5 . Typical Connection Diagram - 14 - [AK5392] 1997/11 ...

Page 15

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK5392 requires careful attention to power supply and grounding arrangements. Analog ground and digital ground should be separate and connected together near to where the supplies are brought onto the printed ...

Page 16

ASAHI KASEI Figure 6 shows a input buffer circuit example. This is a full-differential input buffer circuit with an inverted-amp (gain: -10dB). The capacitor of 2200pF between VREF+/- decreases the clock feed through noise of modulator. And the resistor of ...

Page 17

ASAHI KASEI 28pin SOP (Unit: mm) Package & Lead frame material Package molding compound : Lead frame material : Lead frame surface treatment : 0188-E-01 PACKAGE Epoxy Cu Solder plate - 17 - [AK5392] 1997/11 ...

Page 18

ASAHI KASEI Contents of XXXBYYYYC XXXB: Lot #(X:numbers,B:alphabet) YYYYC: Date Code(Y:numbers,C:alphabet) 0188-E-01 MARKING - 18 - [AK5392] 1997/11 ...

Page 19

IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...

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